- See Issue Tracker id-4 "lnxi-patch-4"

- In addition:
	modified apic_id lifting to always lift all CPUs.  This may cause problems with older kernels.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 125 insertions, 192 deletions

diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index da5928ab14..c74b282cb6 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -1,4 +1,5 @@
 /* 2004.12 yhlu add dual core support */
+/* 24 June 2005 Cleaned up dual core support Eric Biederman */
 
 #include <console/console.h>
 #include <cpu/cpu.h>
@@ -14,59 +15,87 @@
 
 static int first_time = 1;
 static int disable_siblings = !CONFIG_LOGICAL_CPUS;
+void amd_sibling_init(device_t cpu, struct node_core_id id)
+{
+	unsigned long i;
+	unsigned siblings, max_siblings;
+
+	/* On the bootstrap processor see if I want sibling cpus enabled */
+	if (first_time) {
+		first_time = 0;
+		get_option(&disable_siblings, "dual_core");
+	}
 
+        siblings = cpuid_ecx(0x80000008) & 0xff;
+	printk_debug("%d Sibling Cores found\n", siblings);
 
-int is_e0_later_in_bsp(int nodeid) 
-{
-	uint32_t val;
-	uint32_t val_old;
-	int e0_later;
-	if(nodeid==0) { // we don't need to do that for node 0 in core0/node0
-		return !is_cpu_pre_e0();
+	/* For now assume all cpus have the same number of siblings */
+	max_siblings = siblings + 1;
+
+	/* Wishlist? make dual cores look like hyperthreading */
+
+	/* See if I am a sibling cpu */
+	if (disable_siblings && (id.coreid != 0)) {
+		cpu->enabled = 0;
 	}
-	// d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
-	device_t dev;
-	dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid,2));
-	if(!dev) return 0;
-	val_old = pci_read_config32(dev, 0x80);
-	val = val_old;
-	val |= (1<<3);
-	pci_write_config32(dev, 0x80, val);
-	val = pci_read_config32(dev, 0x80);
-	e0_later = !!(val & (1<<3));
-	if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
-		pci_write_config32(dev, 0x80, val_old); // restore it
+
+	if (id.coreid == 0) {
+		/* On the primary cpu find the siblings */
+		for (i = 1; i <= siblings; i++) {
+			struct device_path cpu_path;
+			device_t new;
+			/* Build the cpu device path */
+			cpu_path.type = DEVICE_PATH_APIC;
+			cpu_path.u.apic.apic_id = 
+				(0x10 + i*0x10 + id.nodeid);
+			new = alloc_dev(cpu->bus, &cpu_path);
+			if (!new) {
+				continue;
+			}
+			/* Report what I have done */
+			printk_debug("CPU: %s %s\n",
+				dev_path(new), new->enabled?"enabled":"disabled");
+		}
 	}
-	
-	return e0_later;
 }
 
-unsigned int read_nb_cfg_54(void)
+struct node_core_id get_node_core_id(void)
 {
-        msr_t msr;
-        msr = rdmsr(NB_CFG_MSR);
-        return ( ( msr.hi >> (54-32)) & 1);
-}
-
-struct node_core_id get_node_core_id(unsigned int nb_cfg_54) {
         struct node_core_id id;
-        //    get the apicid via cpuid(1) ebx[27:24]
-	if(nb_cfg_54) {
-                // when NB_CFG[54] is set, nodid = ebx[27:25], coreid = ebx[24]
-                        id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
-                        id.nodeid = (id.coreid>>1);
-                        id.coreid &= 1;
-	} else { // single core should be here too
+	unsigned siblings;
+	/* Get the apicid at reset */
+	id.nodeid = (cpuid_ebx(1) >> 24) & 0xff;
+	id.coreid = 0;	
+	/* Find out how many siblings we have */
+	siblings = cpuid_ecx(0x80000008) & 0xff;
+	if (siblings) {
+		unsigned bits;
+		msr_t msr;
+		bits = 0;
+		while ((1 << bits) <= siblings)
+			bits++;
+
+		msr = rdmsr(NB_CFG_MSR);
+		if ((msr.hi >> (54-32)) & 1) {
+		// when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24]
+			id.coreid = id.nodeid & ((1 << bits) - 1);
+			id.nodeid >>= bits;
+		} else {
                 // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]
-                        id.nodeid = (cpuid_ebx(1) >> 24) & 0xf;
-                        id.coreid = (id.nodeid>>3);
-                        id.nodeid &= 7;
+			id.coreid = id.nodeid >> 3;
+			id.nodeid &= 7;
+		}
+	} else {
+		if (!is_cpu_pre_e0()) {
+			id.nodeid >>= 1;
+		}
 	}
-        return id;
+	return id;
+}
 
 
-}
 
+#if 0
 static int get_max_siblings(int nodes)
 {
 	device_t dev;
@@ -169,76 +198,5 @@ unsigned get_apicid_base(unsigned ioapic_num)
 	
 	return apicid_base;
 }
-#if 0
-void amd_sibling_init(device_t cpu)
-{
-	unsigned i, siblings;
-	struct cpuid_result result;
-	unsigned nb_cfg_54;
-	struct node_core_id id;
-
-	/* On the bootstrap processor see if I want sibling cpus enabled */
-	if (first_time) {
-		first_time = 0;
-		get_option(&disable_siblings, "dual_core");
-	}
-	result = cpuid(0x80000008);
-	/* See how many sibling cpus we have */
-	/* Is dualcore supported */
-	siblings = (result.ecx & 0xff);
-	if ( siblings < 1) {
-		return;
-	}
-
-#if 1
-	printk_debug("CPU: %u %d siblings\n",
-		cpu->path.u.apic.apic_id,
-		siblings);
-#endif
 
-	nb_cfg_54 = read_nb_cfg_54(); 
-#if 1
-	id = get_node_core_id(nb_cfg_54); // pre e0 nb_cfg_54 can not be set
-
-	/* See if I am a sibling cpu */
-	//if ((cpu->path.u.apic.apic_id>>(nb_cfg_54?0:3)) & siblings ) { // siblings = 1, 3, 7, 15,....
-	//if ( ( (cpu->path.u.apic.apic_id>>(nb_cfg_54?0:3)) % (siblings+1) ) != 0 ) {
-	if(id.coreid != 0) {
-	        if (disable_siblings) {
-                        cpu->enabled = 0;
-                }
-                return;
-	}
-#endif
-		
-	/* I am the primary cpu start up my siblings */
-
-	for(i = 1; i <= siblings; i++) {
-		struct device_path cpu_path;
-		device_t new;
-		/* Build the cpu device path */
-		cpu_path.type = DEVICE_PATH_APIC;
-		cpu_path.u.apic.apic_id = cpu->path.u.apic.apic_id + i * (nb_cfg_54?1:8);
-
-                /* See if I can find the cpu */
-                new = find_dev_path(cpu->bus, &cpu_path);
-		/* Allocate the new cpu device structure */
-		if(!new) {
-			new = alloc_dev(cpu->bus, &cpu_path);
-			new->enabled = 1;
-			new->initialized = 0;
-		}
-
-#if 1
-		printk_debug("CPU: %u has sibling %u\n", 
-			cpu->path.u.apic.apic_id,
-			new->path.u.apic.apic_id);
-#endif
-		/* Start the new cpu */
-		if(new->enabled && !new->initialized)
-			start_cpu(new);
-	}
-
-}
 #endif
-
diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c
index 1c3b2751a5..9c292b823c 100644
--- a/src/cpu/amd/dualcore/dualcore.c
+++ b/src/cpu/amd/dualcore/dualcore.c
@@ -1,99 +1,74 @@
 /* 2004.12 yhlu add dual core support */
 
-
-#ifndef SET_NB_CFG_54
-#define SET_NB_CFG_54 1
-#endif
-
 #include "cpu/amd/dualcore/dualcore_id.c"
 
-static inline unsigned get_core_num_in_bsp(unsigned nodeid)
+static void do_k8_init_and_stop_secondaries(void)
 {
-        return ((pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0xe8)>>12) & 3);
-}
-
-static inline 
-#if SET_NB_CFG_54 == 1
-		uint8_t
-#else
-		void 
-#endif
-			set_apicid_cpuid_lo(void) {
-#if SET_NB_CFG_54
-	//for pre_e0, even we set nb_cfg_54, but it will still be 0
-	//for e0 later you should use get_node_id(read_nb_cfg_54()) even for single core cpu
-	//get siblings via cpuid(0x80000008) ecx[7:0]
-	#if CONFIG_MAX_PHYSICAL_CPUS != 8
-	if( get_core_num_in_bsp(0) == 0) {
-                /*first node only has one core, pre_e0
-                  all e0 single core installed don't need enable lo too,
-                  So if mixing e0 single core and dual core, 
-                  don't put single core in first socket */
-        	return 0;
-        }
-	#endif
+	struct node_core_id id;
+	device_t dev;
+	unsigned apicid;
+	unsigned max_siblings;
+	msr_t msr;
 	
-	if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0)  { // disable dual_core
-		return 0;
+	/* Skip this if there was a built in self test failure */
+
+	if (is_cpu_pre_e0()) {
+		id.nodeid = lapicid() & 0x7;
+		id.coreid = 0;
+	} else {
+		/* Which cpu are we on? */
+		id = get_node_core_id_x();
+
+		/* Set NB_CFG_MSR
+		 * Linux expect the core to be in the least signficant bits.
+		 */
+		msr = rdmsr(NB_CFG_MSR);
+		msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
+		wrmsr(NB_CFG_MSR, msr);
 	}
 
-		// set the NB_CFG[54]=1; why the OS will be happy with that ???
-        msr_t msr; 
-        msr = rdmsr(NB_CFG_MSR);
-        msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
-        wrmsr(NB_CFG_MSR, msr);
-
-	return 1;
-
-#endif                  
-
-}
-
-static inline void real_start_other_core(unsigned nodeid)
-{
-	uint32_t dword;
-	// set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0
-	dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44);
-	dword |= 1<<27; // NbMcaToMstCpuEn bit
-	pci_write_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44, dword);
-	// set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
-	dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68);
-	dword |= 1<<5;
-	pci_write_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68, dword);
-}
+	/* For now assume all cpus have the same number of siblings */
+	max_siblings = (cpuid_ecx(0x80000008) & 0xff) + 1;
 
-//it is running on core0 of every node
-static inline void start_other_core(unsigned nodeid) {
+	/* Enable extended apic ids */
+	device_t dev_f0 = PCI_DEV(0, 0x18+id.nodeid, 0);
+	unsigned val = pci_read_config32(dev_f0, 0x68);
+	val |= (1 << 18) | (1 << 17);
+	pci_write_config32(dev_f0, 0x68, val);
 
-        if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0)  { // disable dual_core
-                return;
-        }
+	/* Set the lapicid */
+	lapic_write(LAPIC_ID,(0x10 + id.coreid*0x10 + id.nodeid) << 24);
 
-	if( get_core_num() >0) { // defined in dualcore_id.c
-		real_start_other_core(nodeid);
-        }
+	/* Remember the cpuid */
+	if (id.coreid == 0) {
+		dev = PCI_DEV(0, 0x18 + id.nodeid, 2);
+		pci_write_config32(dev, 0x9c, cpuid_eax(1));	
+	}
+	
+	/* Maybe call distinguish_cpu_resets only on the last core? */
+	distinguish_cpu_resets(id.nodeid);
+	if (!boot_cpu()) {
+		stop_this_cpu();
+	}
 }
 
-static inline unsigned get_nodes(void) 
+static void k8_init_and_stop_secondaries(void)
 {
-	return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
-}
-
-//it is running on core0 of node0
-static inline void start_other_cores(void) {
-	unsigned nodes;
-	unsigned nodeid;
+	/* This doesn't work with Cache As Ram because it messes with 
+	   the MTRR state, which breaks the init detection.
+	   do_k8_init_and_stop_secondaries should be usable by CAR code.
+	*/
 
-        if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0)  { // disable dual_core
-                return;
-        }
+	int init_detected;
 
-        nodes = get_nodes();
+	init_detected = early_mtrr_init_detected();
+	amd_early_mtrr_init();
 
-        for(nodeid=0; nodeid<nodes; nodeid++) {
-		if( get_core_num_in_bsp(nodeid) > 0) {
-			real_start_other_core(nodeid);
-		}
+	enable_lapic();
+	init_timer();
+	if (init_detected) {
+		asm volatile ("jmp __cpu_reset");
 	}
 
+	do_k8_init_and_stop_secondaries();
 }
diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c
index feab682851..75d977133a 100644
--- a/src/cpu/amd/dualcore/dualcore_id.c
+++ b/src/cpu/amd/dualcore/dualcore_id.c
@@ -11,8 +11,8 @@ static inline unsigned int read_nb_cfg_54(void)
 }
 
 struct node_core_id {
-	unsigned nodeid;
-	unsigned coreid;
+	unsigned nodeid:8;
+	unsigned coreid:8;
 };
 
 static inline struct node_core_id get_node_core_id(unsigned nb_cfg_54) {