diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/cpu/amd/family_10h-family_15h/fidvid.c | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/amd/family_10h-family_15h/fidvid.c')
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/fidvid.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 428924df34..db58f5dd34 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -95,21 +95,21 @@ b.- prep_fid_change(...) static inline void print_debug_fv(const char *str, u32 val) { -#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) +#if CONFIG(SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, u8 val) { -#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) +#if CONFIG(SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) { -#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) +#if CONFIG(SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } @@ -505,7 +505,7 @@ static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev, } /* TODO: look into C1E state and F3xA0[IdleExitEn]*/ - #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ) + #if CONFIG(SVI_HIGH_FREQ) if (cpuRev & AMD_FAM10_C3) { dword |= SVI_HIGH_FREQ_ON; } @@ -585,7 +585,7 @@ static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev, if (cpuRev & AMD_DR_Bx ) { smaf001 = 0xA6; } else { - #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ) + #if CONFIG(SVI_HIGH_FREQ) if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { smaf001 = 0xF6; } @@ -1036,7 +1036,7 @@ void init_fidvid_stage2(u32 apicid, u32 nodeid) } -#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) +#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST) struct ap_apicid_st { u32 num; // it could use 256 bytes for 64 node quad core system @@ -1055,7 +1055,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp) int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) { -#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) +#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST) struct ap_apicid_st ap_apicidx; u32 i; #endif @@ -1070,8 +1070,8 @@ int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) print_debug_fv("BSP fid = ", fv.common_fid); -#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \ - !IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY) +#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \ + !CONFIG(SET_FIDVID_CORE0_ONLY) /* For all APs (We know the APIC ID of all APs even when the APIC ID is lifted) remote read from AP LAPIC_MSG_REG about max fid. Then calculate the common max fid that can be used for all |