diff options
author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/cpu/amd/family_10h-family_15h/init_cpus.c | |
parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/amd/family_10h-family_15h/init_cpus.c')
-rw-r--r-- | src/cpu/amd/family_10h-family_15h/init_cpus.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 57d4424bb1..76bc6d99e5 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -18,7 +18,7 @@ #include <device/pci_ops.h> #include "init_cpus.h" -#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) +#if CONFIG(HAVE_OPTION_TABLE) #include "option_table.h" #endif #include <pc80/mc146818rtc.h> @@ -30,17 +30,17 @@ #include <southbridge/amd/common/reset.h> -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) +#if CONFIG(SOUTHBRIDGE_AMD_SB700) #include <southbridge/amd/sb700/sb700.h> #endif -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800) +#if CONFIG(SOUTHBRIDGE_AMD_SB800) #include <southbridge/amd/sb800/sb800.h> #endif #include "cpu/amd/car/disable_cache_as_ram.c" -#if IS_ENABLED(CONFIG_PCI_IO_CFG_EXT) +#if CONFIG(PCI_IO_CFG_EXT) static void set_EnableCf8ExtCfg(void) { // set the NB_CFG_MSR[46]=1; @@ -156,7 +156,7 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node, /* get_nodes define in ht_wrapper.c */ nodes = get_nodes(); - if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) || + if (!CONFIG(LOGICAL_CPUS) || read_option(multi_core, 0) != 0) { // 0 means multi core disable_siblings = 1; } else { @@ -186,8 +186,8 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node, for (j = jstart; j <= jend; j++) { ap_apicid = get_boot_apic_id(i, j); -#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) -#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) +#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) +#if !CONFIG(LIFT_BSP_APIC_ID) if ((i != 0) || (j != 0)) /* except bsp */ #endif ap_apicid += CONFIG_APIC_ID_OFFSET; @@ -231,7 +231,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) return result; } -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid); #endif @@ -402,17 +402,17 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) if (!is_fam15h()) set_apicid_cpuid_lo(); set_EnableCf8ExtCfg(); -#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) +#if CONFIG(ENABLE_APIC_EXT_ID) enable_apic_ext_id(id.nodeid); #endif } enable_lapic(); -#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) +#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) u32 initial_apicid = get_initial_apicid(); -#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) +#if !CONFIG(LIFT_BSP_APIC_ID) if (initial_apicid != 0) // other than bsp #endif { @@ -424,7 +424,7 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) lapic_write(LAPIC_ID, dword); } -#if IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) +#if CONFIG(LIFT_BSP_APIC_ID) bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif @@ -477,8 +477,8 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) } } -#if IS_ENABLED(CONFIG_SET_FIDVID) -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) && IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY) +#if CONFIG(SET_FIDVID) +#if CONFIG(LOGICAL_CPUS) && CONFIG(SET_FIDVID_CORE0_ONLY) // Run on all AP for proper FID/VID setup. if (id.coreid == 0) // only need set fid for core0 #endif @@ -501,7 +501,7 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) if (is_fam15h()) { /* core 1 on node 0 is special; to avoid corrupting the * BSP do not alter MTRRs on that core */ - if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) fam15_bsp_core1_apicid = CONFIG_APIC_ID_OFFSET + 1; else fam15_bsp_core1_apicid = 1; @@ -578,7 +578,7 @@ static void start_node(u8 node) /* Enable routing table */ printk(BIOS_DEBUG, "Start node %02x", node); -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) +#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) /* For FAM10 support, we need to set Dram base/limit for the new node */ pci_write_config32(NODE_MP(node), 0x44, 0); pci_write_config32(NODE_MP(node), 0x40, 3); @@ -1040,7 +1040,7 @@ void cpuSetAMDMSR(uint8_t node_id) } } -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800) +#if CONFIG(SOUTHBRIDGE_AMD_SB700) || CONFIG(SOUTHBRIDGE_AMD_SB800) if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { /* Set up message triggered C1E */ msr = rdmsr(MSR_INTPEND); @@ -1060,7 +1060,7 @@ void cpuSetAMDMSR(uint8_t node_id) if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) { enable_c_states = 0; - if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)) + if (CONFIG(HAVE_ACPI_TABLES)) if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) enable_c_states = !!nvram; @@ -1869,7 +1869,7 @@ void finalize_node_setup(struct sys_info *sysinfo) cpuSetAMDPCI(i); } -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) // Prep each node for FID/VID setup. prep_fid_change(); #endif @@ -1883,6 +1883,6 @@ void finalize_node_setup(struct sys_info *sysinfo) #endif } -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) # include "fidvid.c" #endif |