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author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-31 08:06:12 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-05 09:05:51 +0000 |
commit | 1a5f1c89d752bf906f7428f96c5ff624a1baba97 (patch) | |
tree | 80527bf5c4b6168a59513ee5a1ed7957201d263d /src/cpu/amd/microcode | |
parent | d35c7fe1bff55471c62b11d208cf3a71dec30d6d (diff) | |
download | coreboot-1a5f1c89d752bf906f7428f96c5ff624a1baba97.tar.xz |
cpu/amd: Use common AMD's MSR
This Phase #2 follows the CL done on Phase #1 (Change-Id: I0236e0960cd)
Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29369
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/amd/microcode')
-rw-r--r-- | src/cpu/amd/microcode/microcode.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 68b6953be8..29a550d529 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -17,6 +17,7 @@ #include <stdint.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> #include <cpu/amd/microcode.h> #include <cbfs.h> #include <arch/io.h> @@ -121,7 +122,7 @@ static void apply_microcode_patch(const struct microcode *m) msr.hi = 0; msr.lo = (uint32_t)m; - wrmsr(0xc0010020, msr); + wrmsr(MSR_PATCH_LOADER, msr); UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id); |