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| author | Marc Jones <marc.jones@amd.com> | 2008-04-22 23:09:34 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2008-04-22 23:09:34 +0000 |
| commit | c74e3627233558c62e93beb37efa271f0f353f8d (patch) | |
| tree | 05b9e5780cf75275dbffd1f2c42b79bccf7eea58 /src/cpu/amd/microcode | |
| parent | da4ce6b45157060447cb02fa15349f7de3f531ff (diff) | |
| download | coreboot-c74e3627233558c62e93beb37efa271f0f353f8d.tar.xz | |
Missed this file in the previous check-in, r3248.
Add early MSR and PCI register initialization.
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code
to the generic Fam10 CPU code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/microcode')
0 files changed, 0 insertions, 0 deletions