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authorXavi Drudis Ferran <xdrudis@tinet.cat>2011-02-27 23:50:30 +0000
committerMarc Jones <marc.jones@amd.com>2011-02-27 23:50:30 +0000
commit1d80e5101772220213f64a8845b21fa063710995 (patch)
treec07a38025d2239dff2d6493bea0aa181f32a4fae /src/cpu/amd/model_10xxx
parent9683b1deb2b4489247418c477eb6a5ad59fa0bd1 (diff)
downloadcoreboot-1d80e5101772220213f64a8845b21fa063710995.tar.xz
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3xDC[NbsynPtrAdj], Northbridge/core synchronization FIFO pointer adjust, to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/model_10xxx')
-rw-r--r--src/cpu/amd/model_10xxx/fidvid.c20
1 files changed, 13 insertions, 7 deletions
diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index 60df8b55ce..8f102c5831 100644
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -258,6 +258,17 @@ static void config_power_ctrl_misc_reg(device_t dev) {
}
}
+
+static void config_nb_syn_ptr_adj(device_t dev) {
+ /* Note the following settings are additional from the ported
+ * function setFidVidRegs()
+ */
+ u32 dword = pci_read_config32(dev, 0xDc);
+ dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */
+ pci_write_config32(dev, 0xdc, dword);
+
+}
+
static void prep_fid_change(void)
{
u32 dword;
@@ -281,13 +292,8 @@ static void prep_fid_change(void)
config_clk_power_ctrl_reg0(i);
config_power_ctrl_misc_reg(dev);
-
- /* Note the following settings are additional from the ported
- * function setFidVidRegs()
- */
- dword = pci_read_config32(dev, 0xDc);
- dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */
- pci_write_config32(dev, 0xdc, dword);
+
+ config_nb_syn_ptr_adj(dev);
/* Rev B settings - FIXME: support other revs. */
dword = 0xA0E641E6;