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authorXavi Drudis Ferran <xdrudis@tinet.cat>2011-02-28 03:25:07 +0000
committerMarc Jones <marc.jones@amd.com>2011-02-28 03:25:07 +0000
commit5bcedee0f88fa6390d84f2641dc5b3e109cf6ea3 (patch)
tree599614cb26113b9edcfb20eef8200fed891849ba /src/cpu/amd/model_10xxx
parentce62350d8f5a619c9ce754caeb1e33224e0cce56 (diff)
downloadcoreboot-5bcedee0f88fa6390d84f2641dc5b3e109cf6ea3.tar.xz
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Add an untested step in BKDG 2.4.2.8. I don't have the hardware with Core Performance Boost and I think it's only available in revision E that does not even have a constant yet. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/model_10xxx')
-rw-r--r--src/cpu/amd/model_10xxx/fidvid.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index d621f8ddf2..b1bcac577a 100644
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -65,6 +65,24 @@ static void enable_fid_change(u8 fid)
dword);
}
}
+
+static void applyBoostFIDOffset( device_t dev ) {
+ // BKDG 2.4.2.8
+ // revision E only, but E is apparently not supported yet, therefore untested
+ if ((cpuid_edx(0x80000007) & CPB_MASK)
+ && ((cpuid_ecx(0x80000008) & NC_MASK) ==5) ) {
+ u32 core = get_node_core_id_x().coreid;
+ u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3;
+ msr_t msr = rdmsr(PS_REG_BASE);
+ u32 cpuFid = msr.lo & PS_CPU_FID_MASK;
+ cpuFid = cpuFid + asymetricBoostThisCore;
+ msr.lo &= ~PS_CPU_FID_MASK;
+ msr.lo |= cpuFid ;
+ wrmsr(PS_REG_BASE , msr);
+
+ }
+}
+
static void enableNbPState1( device_t dev ) {
u32 cpuRev = mctGetLogicalCPUID(0xFF);
if (cpuRev & AMD_FAM10_C3) {
@@ -872,7 +890,9 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid)
pci_write_config32(dev, 0xA0, dtemp);
dualPlaneOnly(dev);
+ applyBoostFIDOffset(dev);
enableNbPState1(dev);
+
finalPstateChange();
/* Set TSC to tick at the P0 ndfid rate */