Remove AMD special case for LAPIC based udelay()

- Optionally override FSB clock detection in generic
  LAPIC code with constant value.
- Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz
- compile LAPIC code for romstage, too
- Remove #include ".../apic_timer.c" in AMD based mainboards
- Remove custom udelay implementation from intel northbridges' romstages

Future work:
- remove the compile time special case
  (requires some cpuid based switching)
- drop northbridge udelay implementations (i945, i5000) if
  not required anymore (eg. can SMM use the LAPIC timer?)

Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1618
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

3 files changed, 5 insertions, 56 deletions

diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
index 0254cf239c..c5bdb4a5f8 100644
--- a/src/cpu/amd/model_10xxx/Kconfig
+++ b/src/cpu/amd/model_10xxx/Kconfig
@@ -4,6 +4,7 @@ config CPU_AMD_MODEL_10XXX
 	select SSE2
 	select MMCONF_SUPPORT_DEFAULT
 	select TSC_SYNC_LFENCE
+	select UDELAY_LAPIC
 
 if CPU_AMD_MODEL_10XXX
 config CPU_ADDR_BITS
@@ -56,6 +57,10 @@ config SET_FIDVID_CORE_RANGE
 
 endif	# SET_FIDVID
 
+config UDELAY_LAPIC_FIXED_FSB
+	int
+	default 200
+
 config UPDATE_CPU_MICROCODE
 	bool
 	default y
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index c9becbdb6e..81c565b621 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -1,4 +1,3 @@
 ramstage-y += model_10xxx_init.c
 ramstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c
-ramstage-y += apic_timer.c
 ramstage-y += processor_name.c
diff --git a/src/cpu/amd/model_10xxx/apic_timer.c b/src/cpu/amd/model_10xxx/apic_timer.c
deleted file mode 100644
index d961da795b..0000000000
--- a/src/cpu/amd/model_10xxx/apic_timer.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <stdint.h>
-#include <delay.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
-
-/* NOTE: We use the APIC TIMER register is to hold flags for AP init during
- * pre-memory init (__PRE_RAM__). Don't use init_timer() and  udelay is
- * redirected to udelay_tsc().
- */
-
-
-void init_timer(void)
-{
-	/* Set the apic timer to no interrupts and periodic mode */
-	lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
-
-	/* Set the divider to 1, no divider */
-	lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
-
-	/* Set the initial counter to 0xffffffff */
-	lapic_write(LAPIC_TMICT, 0xffffffff);
-
-}
-
-
-void udelay(u32 usecs)
-{
-	u32 start, value, ticks;
-	/* Calculate the number of ticks to run, our FSB runs a 200Mhz */
-	ticks = usecs * 200;
-	start = lapic_read(LAPIC_TMCCT);
-	do {
-		value = lapic_read(LAPIC_TMCCT);
-	} while((start - value) < ticks);
-
-}