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| author | Patrick Georgi <patrick.georgi@secunet.com> | 2012-11-20 11:53:47 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-27 23:51:52 +0100 |
| commit | e135ac5a7ea69b6edcb89345019212f5de412b1e (patch) | |
| tree | 408611a9f2846867f9731af53b1f08dd32eb6851 /src/cpu/amd/model_fxx | |
| parent | bdc1816b2379bdf569ac6746172bba41e1307917 (diff) | |
| download | coreboot-e135ac5a7ea69b6edcb89345019212f5de412b1e.tar.xz | |
Remove AMD special case for LAPIC based udelay()
- Optionally override FSB clock detection in generic
LAPIC code with constant value.
- Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz
- compile LAPIC code for romstage, too
- Remove #include ".../apic_timer.c" in AMD based mainboards
- Remove custom udelay implementation from intel northbridges' romstages
Future work:
- remove the compile time special case
(requires some cpuid based switching)
- drop northbridge udelay implementations (i945, i5000) if
not required anymore (eg. can SMM use the LAPIC timer?)
Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1618
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd/model_fxx')
| -rw-r--r-- | src/cpu/amd/model_fxx/Kconfig | 5 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/apic_timer.c | 29 |
3 files changed, 5 insertions, 30 deletions
diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index 28beacfa45..fb094b1a5d 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -4,6 +4,7 @@ config CPU_AMD_MODEL_FXX select SSE select SSE2 select TSC_SYNC_LFENCE + select UDELAY_LAPIC if CPU_AMD_MODEL_FXX config UDELAY_IO @@ -23,6 +24,10 @@ config HW_SCRUBBER bool default n +config UDELAY_LAPIC_FIXED_FSB + int + default 200 + if SET_FIDVID config SET_FIDVID_DEBUG bool diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc index 99c09c8395..e016235f7e 100644 --- a/src/cpu/amd/model_fxx/Makefile.inc +++ b/src/cpu/amd/model_fxx/Makefile.inc @@ -1,6 +1,5 @@ # no conditionals here. If you include this file from a socket, then you get all the binaries. ramstage-y += model_fxx_init.c -ramstage-y += apic_timer.c ramstage-y += model_fxx_update_microcode.c ramstage-y += processor_name.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += powernow_acpi.c diff --git a/src/cpu/amd/model_fxx/apic_timer.c b/src/cpu/amd/model_fxx/apic_timer.c deleted file mode 100644 index 6eb99a4eba..0000000000 --- a/src/cpu/amd/model_fxx/apic_timer.c +++ /dev/null @@ -1,29 +0,0 @@ -#include <stdint.h> -#include <delay.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> - -void init_timer(void) -{ - /* Set the apic timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); - -} - -void udelay(unsigned usecs) -{ - uint32_t start, value, ticks; - /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ - ticks = usecs * 200; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); - -} |