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authorarch import user (historical) <svn@openbios.org>2005-07-06 17:11:02 +0000
committerarch import user (historical) <svn@openbios.org>2005-07-06 17:11:02 +0000
commit577f185d382c8130f20f0ee7e8466ed8bbebbacc (patch)
treec3f330ea32887ab26c50cc0fd774cd6f5d0b0d2d /src/cpu/amd/model_gx1
parentfcb591ac680f2b82aacb01e63a4ab91724e1e464 (diff)
downloadcoreboot-577f185d382c8130f20f0ee7e8466ed8bbebbacc.tar.xz
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-29
Creator: Hamish Guthrie <hamish@prodigi.ch> Added NSC pc97317 super-io and added fill character option to config/Options.lb to speed up flash programming git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/model_gx1')
-rw-r--r--src/cpu/amd/model_gx1/cpu_setup.inc2
-rw-r--r--src/cpu/amd/model_gx1/gx_setup.inc2
-rw-r--r--src/cpu/amd/model_gx1/model_gx1_init.c101
3 files changed, 103 insertions, 2 deletions
diff --git a/src/cpu/amd/model_gx1/cpu_setup.inc b/src/cpu/amd/model_gx1/cpu_setup.inc
index adb8cdc267..d701f8d226 100644
--- a/src/cpu/amd/model_gx1/cpu_setup.inc
+++ b/src/cpu/amd/model_gx1/cpu_setup.inc
@@ -8,7 +8,7 @@
/* USES: esi, ecx, eax */
-#include "gx1def.h"
+#include <cpu/amd/gx1def.h>
movl %eax, %ebp /* preserve bist */
diff --git a/src/cpu/amd/model_gx1/gx_setup.inc b/src/cpu/amd/model_gx1/gx_setup.inc
index 60c2bb02d0..6d0e289120 100644
--- a/src/cpu/amd/model_gx1/gx_setup.inc
+++ b/src/cpu/amd/model_gx1/gx_setup.inc
@@ -6,7 +6,7 @@
Setup the GX_BASE registers on a National Semiconductor Geode CPU
*/
-#include "gx1def.h"
+#include <cpu/amd/gx1def.h>
movl %eax, %ebp /* Preserve bist */
diff --git a/src/cpu/amd/model_gx1/model_gx1_init.c b/src/cpu/amd/model_gx1/model_gx1_init.c
new file mode 100644
index 0000000000..b5179565db
--- /dev/null
+++ b/src/cpu/amd/model_gx1/model_gx1_init.c
@@ -0,0 +1,101 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/cache.h>
+
+#if 0
+#include <cpu/amd/gx1def.h>
+#include <arch/io.h>
+
+static void gx1_cpu_setup(void)
+{
+ unsigned char rreg;
+ unsigned char cpu_table[] = {
+ 0xc1, 0x00, /* NO SMIs */
+ 0xc3, 0x14, /* Enable CPU config register */
+ 0x20, 0x00, /* */
+ 0xb8, GX_BASE>>30, /* Enable GXBASE address */
+ 0xc2, 0x00,
+ 0xe8, 0x98,
+ 0xc3, 0xf8, /* Enable CPU config register */
+ 0x00, 0x00
+ };
+ unsigned char *cPtr = cpu_table;
+
+ while(rreg = *cPtr++) {
+ unsigned char rval = *cPtr++;
+ outb(rreg, 0x22);
+ outb(rval, 0x23);
+ }
+
+ outb(0xff, 0x22); /* DIR1 -- Identification register 1 */
+ if(inb(0x23) > 0x63) { /* Rev greater than R3 */
+ outb(0xe8, 0x22);
+ outb(inb(0x23) | 0x20, 0x23); /* Enable FPU Fast Mode */
+
+ outb(0xf0, 0x22);
+ outb(inb(0x23) | 0x02, 0x23); /* Incrementor on */
+
+ outb(0x20, 0x22);
+ outb(inb(0x23) | 0x24, 0x23); /* Bit 5 must be on */
+ /* Bit 2 Incrementor margin 10 */
+
+ }
+}
+
+static void gx1_gx_setup(void)
+{
+unsigned long gx_setup_table[] = {
+ GX_BASE + DC_UNLOCK, DC_UNLOCK_MAGIC,
+ GX_BASE + DC_GENERAL_CFG, 0,
+ GX_BASE + DC_UNLOCK, 0,
+ GX_BASE + BC_DRAM_TOP, 0x3fffffff,
+ GX_BASE + BC_XMAP_1, 0x60,
+ GX_BASE + BC_XMAP_2, 0,
+ GX_BASE + BC_XMAP_3, 0,
+ GX_BASE + MC_BANK_CFG, 0x00700070,
+ GX_BASE + MC_MEM_CNTRL1, XBUSARB,
+ GX_BASE + MC_GBASE_ADD, 0xff,
+ 0, 0
+ };
+
+unsigned long *gxPtr = gx_setup_table;
+unsigned long *gxdPtr;
+unsigned long addr;
+
+ while(addr = *gxPtr++) {
+ gxdPtr = (unsigned long *)addr;
+ *gxdPtr = *gxPtr++;
+ }
+}
+#endif
+
+static void model_gx1_init(device_t dev)
+{
+#if 0
+ gx1_cpu_setup();
+ gx1_gx_setup();
+#endif
+ /* Turn on caching if we haven't already */
+ x86_enable_cache();
+
+ /* Enable the local cpu apics */
+ setup_lapic();
+};
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_gx1_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_CYRIX, 0x0540 },
+ { 0, 0 },
+};
+
+static struct cpu_driver driver __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};