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authorRon Minnich <Ron Minnich>2006-07-28 16:06:16 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-07-28 16:06:16 +0000
commit5e9dc231209c1a293b5a92a9ea78eb07ce0a3086 (patch)
tree00c90e50087fba91bf5fb2cab050b3191b1daf46 /src/cpu/amd/model_lx
parente534daa05ae7057ad615e15fa3021b19f4850fd0 (diff)
downloadcoreboot-5e9dc231209c1a293b5a92a9ea78eb07ce0a3086.tar.xz
This patch adds support for the AMD LX cpu.
There is one global change to pci_ids.h. The rest are changes for LX. I ran abuild and it is ok. Not all artec design changes are included as some of them would adversely affect other mainboards. Indrek will need to test. Signed-off-by: Ron Minnich Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec design. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/model_lx')
-rw-r--r--src/cpu/amd/model_lx/Config.lb8
-rw-r--r--src/cpu/amd/model_lx/cpubug.c391
-rw-r--r--src/cpu/amd/model_lx/cpureginit.c251
-rw-r--r--src/cpu/amd/model_lx/model_lx_init.c47
-rw-r--r--src/cpu/amd/model_lx/syspreinit.c22
-rw-r--r--src/cpu/amd/model_lx/vsmsetup.c855
6 files changed, 1574 insertions, 0 deletions
diff --git a/src/cpu/amd/model_lx/Config.lb b/src/cpu/amd/model_lx/Config.lb
new file mode 100644
index 0000000000..43c6254061
--- /dev/null
+++ b/src/cpu/amd/model_lx/Config.lb
@@ -0,0 +1,8 @@
+dir /cpu/x86/tsc
+dir /cpu/x86/fpu
+dir /cpu/x86/mmx
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+driver model_lx_init.o
+object cpubug.o
+object vsmsetup.o \ No newline at end of file
diff --git a/src/cpu/amd/model_lx/cpubug.c b/src/cpu/amd/model_lx/cpubug.c
new file mode 100644
index 0000000000..4bbab3f933
--- /dev/null
+++ b/src/cpu/amd/model_lx/cpubug.c
@@ -0,0 +1,391 @@
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/amd/lxdef.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/cache.h>
+
+
+#if 0
+void
+bug645(void){
+ msr_t msr;
+ rdmsr(CPU_ID_CONFIG);
+ msr.whatever |= ID_CONFIG_SERIAL_SET;
+ wrmsr(msr);
+}
+
+void
+bug573(void){
+ msr_t msr;
+
+ msr = rdmsr(MC_GLD_MSR_PM);
+ msr.eax &= 0xfff3;
+ wrmsr(MC_GLD_MSR_PM);
+}
+#endif
+
+/**************************************************************************
+ *
+ * pcideadlock
+ *
+ * Bugtool #465 and #609
+ * PCI cache deadlock
+ * There is also fix code in cache and PCI functions. This bug is very is pervasive.
+ *
+ * Entry:
+ * Exit:
+ * Modified:
+ *
+ **************************************************************************/
+static void
+pcideadlock(void)
+{
+ msr_t msr;
+
+ /*
+ * forces serialization of all load misses. Setting this bit prevents the
+ * DM pipe from backing up if a read request has to be held up waiting
+ * for PCI writes to complete.
+ */
+ msr = rdmsr(CPU_DM_CONFIG0);
+ msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
+ msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
+ msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
+ wrmsr(CPU_DM_CONFIG0, msr);
+
+ /* interlock instruction fetches to WS regions with data accesses.
+ * This prevents an instruction fetch from going out to PCI if the
+ * data side is about to make a request.
+ */
+ msr = rdmsr(CPU_IM_CONFIG);
+ msr.lo |= IM_CONFIG_LOWER_QWT_SET;
+ wrmsr(CPU_IM_CONFIG, msr);
+
+ /* write serialize memory hole to PCI. Need to unWS when something is
+ * shadowed regardless of cachablility.
+ */
+ msr.lo = 0x021212121;
+ msr.hi = 0x021212121;
+ wrmsr( CPU_RCONF_A0_BF, msr);
+ wrmsr( CPU_RCONF_C0_DF, msr);
+ wrmsr( CPU_RCONF_E0_FF, msr);
+}
+
+/****************************************************************************
+ *
+ * CPUbug784
+ *
+ * Bugtool #784 + #792
+ *
+ * Fix CPUID instructions for < 3.0 CPUs
+ *
+ * Entry:
+ * Exit:
+ * Modified:
+ *
+ ****************************************************************************/
+
+void bug784(void)
+{
+ msr_t msr;
+ //static char *name = "Geode by NSC";
+
+ /* we'll do this the stupid way, for now, but that's the string they want. NO ONE KNOWS why you
+ * would do this -- the OS can figure this type of stuff out!
+ */
+ msr = rdmsr(0x3006);
+ msr.hi = 0x646f6547;
+ wrmsr(0x3006, msr);
+
+ msr = rdmsr(0x3007);
+ msr.hi = 0x79622065;
+ msr.lo = 0x43534e20;
+ wrmsr(0x3007, msr);
+
+ msr = rdmsr(0x3002);
+ wrmsr(0x3008, msr);
+
+ /* More CPUID to match AMD better. #792*/
+ msr = rdmsr(0x3009);
+ msr.hi = 0x0C0C0A13D;
+ msr.lo = 0x00000000;
+ wrmsr(0x3009, msr);
+}
+
+/* cpubug 1398: enable MC if we KNOW we have DDR*/
+/**************************************************************************
+ *
+ * CPUbugIAENG1398
+ *
+ * ClearQuest #IAENG1398
+ * The MC can not be enabled with SDR memory but can for DDR. Enable for
+ * DDR here if the setup token is "Default"
+ * Add this back to core by default once 2.0 CPUs are not supported.
+ * Entry:
+ * Exit:
+ * Modified:
+ *
+ **************************************************************************/
+void eng1398(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(MSR_GLCP+0x17);
+ if ((msr.lo & 0xff) <= CPU_REV_2_0) {
+ msr = rdmsr(GLCP_SYS_RSTPLL);
+ if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
+ return;
+ }
+
+ /* no CMOS/NVRAM to check, so enable MC Clock Gating */
+ msr = rdmsr(MC_GLD_MSR_PM);
+ msr.lo |= 3; /* enable MC clock gating.*/
+ wrmsr(MC_GLD_MSR_PM, msr);
+}
+
+/***************************************************************************
+ *
+ * CPUbugIAENG2900
+ *
+ * Clear Quest IAENG00002900, VSS 118.150
+ *
+ * BTB issue causes blue screen in windows, but the fix is required
+ * for all operating systems.
+ *
+ * Entry:
+ * Exit:
+ * Modified:
+ *
+ **************************************************************************/
+void
+eng2900(void)
+{
+ msr_t msr;
+
+ printk_debug("CPU_BUG:%s\n", __FUNCTION__);
+ /* Clear bit 43, disables the sysenter/sysexit in CPUID3 */
+ msr = rdmsr(0x3003);
+ msr.hi &= 0xFFFFF7FF;
+ wrmsr(0x3003, msr);
+
+ /* change this value to zero if you need to disable this BTB SWAPSiF. */
+ if (1) {
+
+ /* Disable enable_actions in DIAGCTL while setting up GLCP */
+ msr.hi = 0;
+ msr.lo = 0;
+ wrmsr(MSR_GLCP + 0x005f, msr);
+
+ /* Changing DBGCLKCTL register to GeodeLink */
+ msr.hi = 0;
+ msr.lo = 0;
+ wrmsr(MSR_GLCP + 0x0016, msr);
+
+ msr.hi = 0;
+ msr.lo = 2;
+ wrmsr(MSR_GLCP + 0x0016, msr);
+
+ /* The code below sets up the CPU to stall for 4 GeodeLink
+ * clocks when CPU is snooped. Because setting XSTATE to 0
+ * overrides any other XSTATE action, the code will always
+ * stall for 4 GeodeLink clocks after a snoop request goes
+ * away even if it occured a clock or two later than a
+ * different snoop; the stall signal will never 'glitch high'
+ * for only one or two CPU clocks with this code.
+ */
+
+ /* Send mb0 port 3 requests to upper GeodeLink diag bits
+ [63:32] */
+ msr.hi = 0;
+ msr.lo = 0x80338041;
+ wrmsr(MSR_GLIU0 + 0x2005, msr);
+
+ /* set5m watches request ready from mb0 to CPU (snoop) */
+ msr.hi = 0x5ad68000;
+ msr.lo = 0;
+ wrmsr(MSR_GLCP + 0x0045, msr);
+
+ /* SET4M will be high when state is idle (XSTATE=11) */
+ msr.hi = 0;
+ msr.lo = 0x0140;
+ wrmsr(MSR_GLCP + 0x0044, msr);
+
+ /* SET5n to watch for processor stalled state */
+ msr.hi = 0x2000;
+ msr.lo = 0;
+ wrmsr(MSR_GLCP + 0x004D, msr);
+
+ /* Writing action number 13: XSTATE=0 to occur when CPU is
+ snooped unless we're stalled */
+ msr.hi = 0;
+ msr.lo = 0x00400000;
+ wrmsr(MSR_GLCP + 0x0075, msr);
+
+ /* Writing action number 11: inc XSTATE every GeodeLink clock
+ unless we're idle */
+ msr.hi = 0;
+ msr.lo = 0x30000;
+ wrmsr(MSR_GLCP + 0x0073, msr);
+
+ /* Writing action number 5: STALL_CPU_PIPE when exitting idle
+ state or not in idle state */
+ msr.hi = 0;
+ msr.lo = 0x00430000;
+ wrmsr(MSR_GLCP + 0x006D, msr);
+
+ /* Writing DIAGCTL Register to enable the stall action and to
+ let set5m watch the upper GeodeLink diag bits. */
+ msr.hi = 0;
+ msr.lo = 0x80004000;
+ wrmsr(MSR_GLCP + 0x005f, msr);
+ }
+}
+
+void bug118253(void)
+{
+ /* GLPCI PIO Post Control shouldn't be enabled */
+ msr_t msr;
+
+ msr = rdmsr(GLPCI_SPARE);
+ msr.lo &= ~GLPCI_SPARE_LOWER_PPC_SET;
+ wrmsr(GLPCI_SPARE, msr);
+}
+
+void bug118339(void)
+{
+ /* per AMD, do this always */
+ msr_t msr = {0,0};
+ int msrnum;
+
+ /* Disable enable_actions in DIAGCTL while setting up GLCP */
+ wrmsr(MSR_GLCP + 0x005f, msr);
+
+ /* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */
+ msrnum = MSR_GLCP + 0x042;
+ /* msr.hi = 2d6b8000h */;
+ msr.hi = 0x596b8000;
+ msr.lo = 0x00000a00;
+ wrmsr(msrnum, msr);
+
+ /* SET3M fires if MBUS changed and VG pri is odd */
+ msrnum = MSR_GLCP + 0x043;
+ msr.hi = 0x596b8040;
+ msr.lo = 0;
+ wrmsr(msrnum, msr);
+
+ /* Put VG request data on lower diag bus */
+ msrnum = MSR_GLIU0 + 0x2005;
+ msr.hi = 0;
+ msr.lo = 0x80338041;
+ wrmsr(msrnum, msr);
+
+ /* Increment Y state if SET3M if true */
+ msrnum = MSR_GLCP + 0x074;
+ msr.hi = 0;
+ msr.lo = 0x0000c000;
+ wrmsr(msrnum, msr);
+
+ /* Set up MBUS action to PRI=3 read of MBIU */
+ msrnum = MSR_GLCP + 0x020;
+ msr.hi = 0x0000d863;
+ msr.lo = 0x20002000;
+ wrmsr(msrnum, msr);
+
+ /* Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */
+ msrnum = MSR_GLCP + 0x071;
+ msr.hi = 0;
+ msr.lo = 0x00000c00;
+ wrmsr(msrnum, msr);
+
+ /* Writing DIAGCTL */
+ msrnum = MSR_GLCP + 0x005f;
+ msr.hi = 0;
+ msr.lo = 0x80004000;
+ wrmsr(msrnum, msr);
+
+ /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */
+ /* As per Todd Roberts in PBz1094 and PBz1095 */
+ /* Moved from CPUREG to CPUBUG per Tom Sylla */
+ msrnum = 0x04C000042; /* GLCP SETMCTL Register */;
+ msr = rdmsr(msrnum);
+ msr.hi |= 8; /* Bit 35 = MCP_IN */
+ wrmsr(msrnum, msr);
+}
+
+
+
+/****************************************************************************/
+/***/
+/** DisableMemoryReorder*/
+/***/
+/** PBZ 3659:*/
+/** The MC reordered transactions incorrectly and breaks coherency.*/
+/** Disable reording and take a potential performance hit.*/
+/** This is safe to do here and not in MC init since there is nothing*/
+/** to maintain coherency with and the cache is not enabled yet.*/
+/***/
+/***/
+/** Entry:*/
+/** Exit:*/
+/** Modified:*/
+/***/
+/****************************************************************************/
+void disablememoryreadorder(void)
+{
+ msr_t msr;
+ msr = rdmsr(MC_CF8F_DATA);
+
+ msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
+ wrmsr(MC_CF8F_DATA, msr);
+}
+
+void
+cpubug(void)
+{
+ msr_t msr;
+ int rev;
+#if 0 //GX3
+ msr = rdmsr(GLCP_CHIP_REVID);
+
+ rev = msr.lo & 0xff;
+ if (rev < 0x20) {
+ printk_err("%s: rev < 0x20! bailing!\n");
+ return;
+ }
+ printk_debug("Doing cpubug fixes for rev 0x%x\n", rev);
+ switch(rev)
+ {
+ case 0x20:
+ pcideadlock();
+ eng1398();
+ /* cs 5530 bug; ignore
+ bug752();
+ */
+ break;
+ case 0x21:
+ pcideadlock();
+ eng1398();
+ eng2900();
+ bug118339();
+ break;
+ case 0x22:
+ case 0x30:
+ break;
+ default:
+ printk_err("unknown rev %x, bailing\n", rev);
+ return;
+ }
+ bug784();
+ bug118253();
+ disablememoryreadorder();
+ printk_debug("Done cpubug fixes \n");
+#endif
+
+}
diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c
new file mode 100644
index 0000000000..58576c2fcd
--- /dev/null
+++ b/src/cpu/amd/model_lx/cpureginit.c
@@ -0,0 +1,251 @@
+
+
+/* ***************************************************************************/
+/* **/
+/* * BIST */
+/* **/
+/* * GX2 BISTs need to be run before BTB or caches are enabled.*/
+/* * BIST result left in registers on failure to be checked with FS2.*/
+/* **/
+/* ***************************************************************************/
+static void
+BIST(void){
+ int msrnum;
+ msr_t msr;
+
+ /* DM*/
+ msrnum = CPU_DM_CONFIG0;
+ msr = rdmsr(msrnum);
+ msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
+ wrmsr(msrnum, msr);
+
+ msr.lo = 0x00000003F;
+ msr.hi = 0x000000000;
+ msrnum = CPU_DM_BIST;
+ wrmsr(msrnum, msr);
+
+ outb(POST_CPU_DM_BIST_FAILURE, 0x80); /* 0x29*/
+ msr = rdmsr(msrnum); /* read back for pass fail*/
+ msr.lo &= 0x0F3FF0000;
+ if (msr.lo != 0xfeff0000)
+ goto BISTFail;
+
+ msrnum = CPU_DM_CONFIG0;
+ msr = rdmsr(msrnum);
+ msr.lo &= ~ DM_CONFIG0_LOWER_DCDIS_SET;
+ wrmsr(msrnum, msr);
+
+ /* FPU*/
+ msr.lo = 0x000000131;
+ msr.hi = 0;
+ msrnum = CPU_FP_UROM_BIST;
+ wrmsr(msrnum, msr);
+
+ outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/
+ inb(0x80); /* IO delay*/
+ msr = rdmsr(msrnum); /* read back for pass fail*/
+ while ((msr.lo&0x884) != 0x884)
+ msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/
+ if ((msr.lo&0x642) != 0x642)
+ goto BISTFail;
+
+ msr.lo = msr.hi = 0; /* clear FPU BIST bits*/
+ msrnum = CPU_FP_UROM_BIST;
+ wrmsr(msrnum, msr);
+
+
+ /* BTB*/
+ msr.lo = 0x000000303;
+ msr.hi = 0x000000000;
+ msrnum = CPU_PF_BTBRMA_BIST;
+ wrmsr(msrnum, msr);
+
+ outb(POST_CPU_BTB_BIST_FAILURE , 0x80); /* 0x8A*/
+ msr = rdmsr(msrnum); /* read back for pass fail*/
+ if ((msr.lo & 0x3030) != 0x3030)
+ goto BISTFail;
+
+ return;
+
+BISTFail:
+ print_err("BIST failed!\n");
+ while(1);
+}
+/* ***************************************************************************/
+/* * cpuRegInit*/
+/* ***************************************************************************/
+void
+cpuRegInit (void){
+ int msrnum;
+ msr_t msr;
+
+ //GX3 suspend: what is desired?
+
+ /* Enable Suspend on Halt*/
+ /*msrnum = CPU_XC_CONFIG;
+ msr = rdmsr(msrnum);
+ msr.lo |= XC_CONFIG_SUSP_ON_HLT;
+ wrmsr(msrnum, msr);*/
+
+ /* ENable SUSP and allow TSC to run in Suspend */
+ /* to keep speed detection happy*/
+ /*msrnum = CPU_BC_CONF_0;
+ msr = rdmsr(msrnum);
+ msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
+ wrmsr(msrnum, msr);*/
+
+ /* Setup throttling to proper mode if it is ever enabled.*/
+ msrnum = 0x04C00001E;
+ msr.hi = 0x000000000;
+ msr.lo = 0x00000603C;
+ wrmsr(msrnum, msr); // GX3 OK +/-
+
+
+/* Only do this if we are building for 5535*/
+/* */
+/* FooGlue Setup*/
+/* */
+#if 0
+ /* Enable CIS mode B in FooGlue*/
+ msrnum = MSR_FG + 0x10;
+ msr = rdmsr(msrnum);
+ msr.lo &= ~3;
+ msr.lo |= 2; /* ModeB*/
+ wrmsr(msrnum, msr);
+#endif
+
+/* */
+/* Disable DOT PLL. Graphics init will enable it if needed.*/
+/* */
+
+// GX3: Disable DOT PLL? No. Lets tick.
+
+/* msrnum = GLCP_DOTPLL;
+ msr = rdmsr(msrnum);
+ msr.lo |= DOTPPL_LOWER_PD_SET;
+ wrmsr(msrnum, msr); */
+
+/* */
+/* Enable RSDC*/
+/* */
+ msrnum = 0x1301 ;
+ msr = rdmsr(msrnum);
+ msr.lo |= 0x08;
+ wrmsr(msrnum, msr); //GX3 OK
+
+
+/* */
+/* BIST*/
+/* */
+ /*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/
+ {
+// BIST();
+ }
+
+
+/* */
+/* Enable BTB*/
+/* */
+ /* I hate to put this check here but it doesn't really work in cpubug.asm*/
+
+//GX3: BTB is enabled by default
+
+/* msrnum = MSR_GLCP+0x17;
+ msr = rdmsr(msrnum);
+ if (msr.lo >= CPU_REV_2_1){
+ msrnum = CPU_PF_BTB_CONF;
+ msr = rdmsr(msrnum);
+ msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET;
+ wrmsr(msrnum, msr);
+ }
+
+ */
+
+/* */
+/* FPU impercise exceptions bit*/
+/* */
+ /*if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {*/
+
+
+
+// GX3: FPU impercise exceptions bit - what's that?
+/* {
+ msrnum = CPU_FPU_MSR_MODE;
+ msr = rdmsr(msrnum);
+ msr.lo |= FPU_IE_SET;
+ wrmsr(msrnum, msr);
+ }
+
+ */
+
+#if 0
+ /* */
+ /* Cache Overides*/
+ /* */
+ /* This code disables the data cache. Don't execute this
+ * unless you're testing something.
+ */
+ /* Allow NVRam to override DM Setup*/
+ /*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
+ {
+
+ msrnum = CPU_DM_CONFIG0;
+ msr = rdmsr(msrnum);
+ msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
+ wrmsr(msrnum, msr);
+ }
+ /* This code disables the instruction cache. Don't execute
+ * this unless you're testing something.
+ */
+ /* Allow NVRam to override IM Setup*/
+ /*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/
+ {
+ msrnum = CPU_IM_CONFIG;
+ msr = rdmsr(msrnum);
+ msr.lo |= IM_CONFIG_LOWER_ICD_SET;
+ wrmsr(msrnum, msr);
+ }
+#endif
+}
+
+
+
+
+/* ***************************************************************************/
+/* **/
+/* * MTestPinCheckBX*/
+/* **/
+/* * Set MTEST pins to expected values from OPTIONS.INC/NVRAM*/
+/* * This version is called when there isn't a stack available*/
+/* **/
+/* ***************************************************************************/
+static void
+MTestPinCheckBX (void){
+ int msrnum;
+ msr_t msr;
+
+ /*if (getnvram( TOKEN_MTEST_ENABLE) ==TVALUE_DISABLE ) {*/
+ /* return ; */
+ /* } */
+
+ /* Turn on MTEST*/
+ msrnum = MC_CFCLK_DBUG;
+ msr = rdmsr(msrnum);
+ msr.hi |= CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET;
+ wrmsr(msrnum, msr);
+
+ msrnum = GLCP_SYS_RSTPLL /* Get SDR/DDR mode from GLCP*/;
+ msr = rdmsr(msrnum);
+ msr.lo >>= RSTPPL_LOWER_SDRMODE_SHIFT;
+ if (msr.lo & 1) {
+ msrnum = MC_CFCLK_DBUG; /* Turn on SDR MTEST stuff*/
+ msr = rdmsr(msrnum);
+ msr.lo |= CFCLK_LOWER_SDCLK_SET;
+ msr.hi |= CFCLK_UPPER_MTST_DQS_EN_SET;
+ wrmsr(msrnum, msr);
+ }
+
+ /* Lock the cache down here.*/
+ __asm__("wbinvd\n");
+
+}
diff --git a/src/cpu/amd/model_lx/model_lx_init.c b/src/cpu/amd/model_lx/model_lx_init.c
new file mode 100644
index 0000000000..f7787538a9
--- /dev/null
+++ b/src/cpu/amd/model_lx/model_lx_init.c
@@ -0,0 +1,47 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/cache.h>
+
+
+static void vsm_end_post_smi(void)
+{
+ __asm__ volatile (
+ "push %ax\n"
+ "mov $0x5000, %ax\n"
+ ".byte 0x0f, 0x38\n"
+ "pop %ax\n"
+ );
+}
+
+static void model_lx_init(device_t dev)
+{
+ printk_debug("model_lx_init\n");
+
+ /* Turn on caching if we haven't already */
+ x86_enable_cache();
+
+ /* Enable the local cpu apics */
+ //setup_lapic();
+
+ vsm_end_post_smi();
+
+ printk_debug("model_lx_init DONE\n");
+};
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_lx_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_AMD, 0x05A2 },
+ { 0, 0 },
+};
+
+static struct cpu_driver driver __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
diff --git a/src/cpu/amd/model_lx/syspreinit.c b/src/cpu/amd/model_lx/syspreinit.c
new file mode 100644
index 0000000000..e3ad95235d
--- /dev/null
+++ b/src/cpu/amd/model_lx/syspreinit.c
@@ -0,0 +1,22 @@
+/* ***************************************************************************/
+/* **/
+/* * StartTimer1*/
+/* **/
+/* * Entry: none*/
+/* * Exit: Starts Timer 1 for port 61 use*/
+/* * Destroys: Al,*/
+/* **/
+/* ***************************************************************************/
+void
+StartTimer1(void){
+ outb(0x56, 0x43);
+ outb(0x12, 0x41);
+}
+
+void
+SystemPreInit(void){
+
+ /* they want a jump ... */
+ __asm__("jmp .+2\ninvd\njmp.+2\n");
+ StartTimer1();
+}
diff --git a/src/cpu/amd/model_lx/vsmsetup.c b/src/cpu/amd/model_lx/vsmsetup.c
new file mode 100644
index 0000000000..d8381debed
--- /dev/null
+++ b/src/cpu/amd/model_lx/vsmsetup.c
@@ -0,0 +1,855 @@
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#undef __KERNEL__
+#include <arch/io.h>
+#include <string.h>
+#include <cpu/amd/lxdef.h>
+
+/* what a mess this uncompress thing is. I am not at all happy about how this
+ * was done, but can't fix it yet. RGM
+ */
+#warning "Fix the uncompress once linuxbios knows how to do it"
+// This GETBIT is supposed to work on little endian
+// 32bit systems. The algorithm will definitely need
+// some fixing on other systems, but it might not be
+// a problem since the nrv2b binary behaves the same..
+
+#ifndef ENDIAN
+#define ENDIAN 0
+#endif
+#ifndef BITSIZE
+#define BITSIZE 32
+#endif
+
+#define GETBIT_8(bb, src, ilen) \
+ (((bb = bb & 0x7f ? bb*2 : ((unsigned)src[ilen++]*2+1)) >> 8) & 1)
+
+#define GETBIT_LE16(bb, src, ilen) \
+ (bb*=2,bb&0xffff ? (bb>>16)&1 : (ilen+=2,((bb=(src[ilen-2]+src[ilen-1]*256u)*2+1)>>16)&1))
+#define GETBIT_LE32(bb, src, ilen) \
+ (bc > 0 ? ((bb>>--bc)&1) : (bc=31,\
+ bb=*(const uint32_t *)((src)+ilen),ilen+=4,(bb>>31)&1))
+
+#if ENDIAN == 0 && BITSIZE == 8
+#define GETBIT(bb, src, ilen) GETBIT_8(bb, src, ilen)
+#endif
+#if ENDIAN == 0 && BITSIZE == 16
+#define GETBIT(bb, src, ilen) GETBIT_LE16(bb, src, ilen)
+#endif
+#if ENDIAN == 0 && BITSIZE == 32
+#define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen)
+#endif
+
+static unsigned long unrv2b(uint8_t * src, uint8_t * dst)
+{
+ unsigned long ilen = 0, olen = 0, last_m_off = 1;
+ uint32_t bb = 0;
+ unsigned bc = 0;
+ const uint8_t *m_pos;
+ unsigned long file_len = *(unsigned long *) src;
+
+ printk_debug("compressed file len is supposed to be %d bytes\n", file_len);
+ // skip length
+ src += 4;
+ /* FIXME: check olen with the length stored in first 4 bytes */
+
+ for (;;) {
+ unsigned int m_off, m_len;
+ while (GETBIT(bb, src, ilen)) {
+ dst[olen++] = src[ilen++];
+ }
+
+ m_off = 1;
+ do {
+ m_off = m_off * 2 + GETBIT(bb, src, ilen);
+ } while (!GETBIT(bb, src, ilen));
+ if (m_off == 2) {
+ m_off = last_m_off;
+ } else {
+ m_off = (m_off - 3) * 256 + src[ilen++];
+ if (m_off == 0xffffffffU)
+ break;
+ last_m_off = ++m_off;
+ }
+
+ m_len = GETBIT(bb, src, ilen);
+ m_len = m_len * 2 + GETBIT(bb, src, ilen);
+ if (m_len == 0) {
+ m_len++;
+ do {
+ m_len = m_len * 2 + GETBIT(bb, src, ilen);
+ } while (!GETBIT(bb, src, ilen));
+ m_len += 2;
+ }
+ m_len += (m_off > 0xd00);
+
+ m_pos = dst + olen - m_off;
+ dst[olen++] = *m_pos++;
+ do {
+ dst[olen++] = *m_pos++;
+ } while (--m_len > 0);
+ }
+
+ printk_debug("computed len is %d, file len is %d\n", olen, file_len);
+ return olen;
+
+}
+
+/* vsmsetup.c derived from vgabios.c. Derived from: */
+
+/*------------------------------------------------------------ -*- C -*-
+ * 2 Kernel Monte a.k.a. Linux loading Linux on x86
+ *
+ * Erik Arjan Hendriks <hendriks@lanl.gov>
+ *
+ * This version is a derivative of the original two kernel monte
+ * which is (C) 2000 Scyld.
+ *
+ * Copyright (C) 2000 Scyld Computing Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Portions related to the alpha architecture are:
+ *
+ * Copyright(C) 2001 University of California. LA-CC Number 01-67.
+ * This software has been authored by an employee or employees of the
+ * University of California, operator of the Los Alamos National
+ * Laboratory under Contract No. W-7405-ENG-36 with the U.S.
+ * Department of Energy. The U.S. Government has rights to use,
+ * reproduce, and distribute this software. If the software is
+ * modified to produce derivative works, such modified software should
+ * be clearly marked, so as not to confuse it with the version
+ * available from LANL.
+ *
+ * This software may be used and distributed according to the terms
+ * of the GNU General Public License, incorporated herein by
+ * reference to http://www.gnu.org/licenses/gpl.html.
+ *
+ * This software is provided by the author(s) "as is" and any express
+ * or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose
+ * are disclaimed. In no event shall the author(s) be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential
+ * damages (including, but not limited to, procurement of substitute
+ * goods or services; loss of use, data, or profits; or business
+ * interruption) however caused and on any theory of liability,
+ * whether in contract, strict liability, or tort (including
+ * negligence or otherwise) arising in any way out of the use of this
+ * software, even if advised of the possibility of such damage.
+ *
+ * $Id: Exp $
+ *--------------------------------------------------------------------*/
+
+/* Modified to be a self sufficient plug in so that it can be used
+ without reliance on other parts of core Linuxbios
+ (C) 2005 Nick.Barker9@btinternet.com
+
+ Used initially for epia-m where there are problems getting the bios
+ emulator to successfully run this bios.
+*/
+
+/* Declare a temporary global descriptor table - necessary because the
+ Core part of the bios no longer sets up any 16 bit segments */
+__asm__ (
+ /* pointer to original gdt */
+ "gdtarg: \n"
+ " .word gdt_limit \n"
+ " .long gdt \n"
+
+ /* compute the table limit */
+ "__mygdt_limit = __mygdt_end - __mygdt - 1 \n"
+
+ "__mygdtaddr: \n"
+ " .word __mygdt_limit \n"
+ " .long __mygdt \n"
+
+ "__mygdt: \n"
+ /* selgdt 0, unused */
+ " .word 0x0000, 0x0000 \n"
+ " .byte 0x00, 0x00, 0x00, 0x00 \n"
+
+ /* selgdt 8, unused */
+ " .word 0x0000, 0x0000 \n"
+ " .byte 0x00, 0x00, 0x00, 0x00 \n"
+
+ /* selgdt 0x10, flat code segment */
+ " .word 0xffff, 0x0000 \n"
+ " .byte 0x00, 0x9b, 0xcf, 0x00 \n"
+
+ /* selgdt 0x18, flat data segment */
+ " .word 0xffff, 0x0000 \n"
+ " .byte 0x00, 0x93, 0xcf, 0x00 \n"
+
+ /* selgdt 0x20, unused */
+ " .word 0x0000, 0x0000 \n"
+ " .byte 0x00, 0x00, 0x00, 0x00 \n"
+
+ /* selgdt 0x28 16-bit 64k code at 0x00000000 */
+ " .word 0xffff, 0x0000 \n"
+ " .byte 0, 0x9a, 0, 0 \n"
+
+ /* selgdt 0x30 16-bit 64k data at 0x00000000 */
+ " .word 0xffff, 0x0000 \n"
+ " .byte 0, 0x92, 0, 0 \n"
+
+ "__mygdt_end: \n"
+);
+
+/* Declare a pointer to where our idt is going to be i.e. at mem zero */
+__asm__ ("__myidt: \n"
+ /* 16-bit limit */
+ " .word 1023 \n"
+ /* 24-bit base */
+ " .long 0 \n"
+ " .word 0 \n"
+);
+
+/* The address arguments to this function are PHYSICAL ADDRESSES */
+static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm)
+{
+ __asm__ __volatile__ (
+ // paranoia -- does ecx get saved? not sure. This is
+ // the easiest safe thing to do.
+ " pushal \n"
+ /* save the stack */
+ " mov %esp, __stack \n"
+ " jmp 1f \n"
+ "__stack: .long 0 \n"
+ "1:\n"
+ /* get devfn into %ecx */
+ " movl %esp, %ebp \n"
+#if 0
+ /* I'm not happy about that pushal followed by esp-relative references.
+ * just do hard-codes for now
+ */
+ " movl 8(%ebp), %ecx \n"
+ " movl 12(%ebp), %edx \n"
+#endif
+ " movl $0x10000026, %ecx \n"
+ " movl $0x10000028, %edx \n"
+
+ /* load 'our' gdt */
+ " lgdt %cs:__mygdtaddr \n"
+
+ /* This configures CS properly for real mode. */
+ " ljmp $0x28, $__rms_16bit\n"
+ "__rms_16bit: \n"
+ " .code16 \n"
+ /* 16 bit code from here on... */
+
+ /* Load the segment registers w/ properly configured segment
+ * descriptors. They will retain these configurations (limits,
+ * writability, etc.) once protected mode is turned off. */
+ " mov $0x30, %ax \n"
+ " mov %ax, %ds \n"
+ " mov %ax, %es \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+ " mov %ax, %ss \n"
+
+ /* Turn off protection (bit 0 in CR0) */
+ " movl %cr0, %eax \n"
+ " andl $0xFFFFFFFE, %eax \n"
+ " movl %eax, %cr0 \n"
+
+ /* Now really going into real mode */
+ " ljmp $0, $__rms_real\n"
+ "__rms_real: \n"
+
+ /* put the stack at the end of page zero.
+ * that way we can easily share it between real and protected,
+ * since the 16-bit ESP at segment 0 will work for any case. */
+ /* Setup a stack */
+ " mov $0x0, %ax \n"
+ " mov %ax, %ss \n"
+ " movl $0x1000, %eax \n"
+ " movl %eax, %esp \n"
+
+ /* Load our 16 it idt */
+ " xor %ax, %ax \n"
+ " mov %ax, %ds \n"
+ " lidt __myidt \n"
+
+ /* Dump zeros in the other segregs */
+ " mov %ax, %es \n"
+ /* FixMe: Big real mode for gs, fs? */
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+ " mov $0x40, %ax \n"
+ " mov %ax, %ds \n"
+ //" mov %cx, %ax \n"
+ " movl $0x10000026, %ecx \n"
+ " movl $0x10000028, %edx \n"
+
+ /* run VGA BIOS at 0x6000:0020 */
+ " lcall $0x6000, $0x0020\n"
+
+ /* if we got here, just about done.
+ * Need to get back to protected mode */
+ " movl %cr0, %eax \n"
+ " orl $0x0000001, %eax\n" /* PE = 1 */
+ " movl %eax, %cr0 \n"
+
+ /* Now that we are in protected mode jump to a 32 bit code segment. */
+ " data32 ljmp $0x10, $vsmrestart\n"
+ "vsmrestart:\n"
+ " .code32\n"
+ " movw $0x18, %ax \n"
+ " mov %ax, %ds \n"
+ " mov %ax, %es \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+ " mov %ax, %ss \n"
+
+ /* restore proper gdt and idt */
+ " lgdt %cs:gdtarg \n"
+ " lidt idtarg \n"
+
+ ".globl vsm_exit \n"
+ "vsm_exit: \n"
+ " mov __stack, %esp \n"
+ " popal \n"
+ );
+}
+
+__asm__ (".text\n""real_mode_switch_end:\n");
+extern char real_mode_switch_end[];
+
+
+void do_vsmbios(void)
+{
+ device_t dev;
+ unsigned long busdevfn;
+ unsigned int rom = 0;
+ unsigned char *buf;
+ unsigned int size = SMM_SIZE*1024;
+ int i;
+
+ printk_err("do_vsmbios\n");
+ /* clear vsm bios data area */
+ for (i = 0x400; i < 0x500; i++) {
+ *(unsigned char *) i = 0;
+ }
+
+ /* declare rom address here - keep any config data out of the way
+ * of core LXB stuff */
+
+ /* this is the base of rom on the GX2 at present. At some point, this has to be
+ * much better parameterized
+ */
+ //rom = 0xfff80000;
+ //rom = 0xfffc0000;
+ /* the VSA starts at the base of rom - 64 */
+ //rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024);
+
+ rom = 0xfffc0000;
+
+ buf = (unsigned char *) 0x60000;
+ unrv2b((uint8_t *)rom, buf);
+ printk_debug("buf %p *buf %d buf[256k] %d\n",
+ buf, buf[0], buf[SMM_SIZE*1024]);
+ printk_debug("buf[0x20] signature is %x:%x:%x:%x\n",
+ buf[0x20] ,buf[0x21] ,buf[0x22],buf[0x23]);
+ /* check for post code at start of vsainit.bin. If you don't see it,
+ don't bother. */
+ if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) ||
+ (buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) {
+ printk_err("do_vsmbios: no vsainit.bin signature, skipping!\n");
+ return;
+ }
+
+ //memcpy((void *) 0x60000, buf, size);
+
+ //for (i = 0; i < 0x800000; i++)
+ // outb(0xaa, 0x80);
+
+ /* ecx gets smm, edx gets sysm */
+ printk_err("Call real_mode_switch_call_vsm\n");
+ real_mode_switch_call_vsm(0x10000026, 0x10000028);
+
+ /* restart timer 1 */
+ outb(0x56, 0x43);
+ outb(0x12, 0x41);
+}
+
+
+// we had hoped to avoid this.
+// this is a stub IDT only. It's main purpose is to ignore calls
+// to the BIOS.
+// no longer. Dammit. We have to respond to these.
+struct realidt {
+ unsigned short offset, cs;
+};
+
+// from a handy writeup that andrey found.
+
+// handler.
+// There are some assumptions we can make here.
+// First, the Top Of Stack (TOS) is located on the top of page zero.
+// we can share this stack between real and protected mode.
+// that simplifies a lot of things ...
+// we'll just push all the registers on the stack as longwords,
+// and pop to protected mode.
+// second, since this only ever runs as part of linuxbios,
+// we know all the segment register values -- so we don't save any.
+// keep the handler that calls things small. It can do a call to
+// more complex code in linuxbios itself. This helps a lot as we don't
+// have to do address fixup in this little stub, and calls are absolute
+// so the handler is relocatable.
+void handler(void)
+{
+ __asm__ __volatile__ (
+ " .code16 \n"
+ "idthandle: \n"
+ " pushal \n"
+ " movb $0, %al \n"
+ " ljmp $0, $callbiosint16\n"
+ "end_idthandle: \n"
+ " .code32 \n"
+ );
+}
+
+void debughandler(void)
+{
+ __asm__ __volatile__ (
+ " .code16 \n"
+ "debughandle: \n"
+ " pushw %cx \n"
+ " movw $250, %cx \n"
+ "dbh1: \n"
+ " loop dbh1 \n"
+ " popw %cx \n"
+ " iret \n"
+ "end_debughandle: \n"
+ ".code32 \n"
+ );
+}
+
+// Calling conventions. The first C function is called with this stuff
+// on the stack. They look like value parameters, but note that if you
+// modify them they will go back to the INTx function modified.
+// the C function will call the biosint function with these as
+// REFERENCE parameters. In this way, we can easily get
+// returns back to the INTx caller (i.e. vgabios)
+void callbiosint(void)
+{
+ __asm__ __volatile__ (
+ " .code16 \n"
+ "callbiosint16: \n"
+ " push %ds \n"
+ " push %es \n"
+ " push %fs \n"
+ " push %gs \n"
+ // clean up the int #. To save space we put it in the lower
+ // byte. But the top 24 bits are junk.
+ " andl $0xff, %eax\n"
+ // this push does two things:
+ // - put the INT # on the stack as a parameter
+ // - provides us with a temp for the %cr0 mods.
+ " pushl %eax \n"
+ " movb $0xbb, %al\n"
+ " outb %al, $0x80\n"
+ " movl %cr0, %eax\n"
+ " orl $0x00000001, %eax\n" /* PE = 1 */
+ " movl %eax, %cr0\n"
+ /* Now that we are in protected mode jump to a 32 bit code segment. */
+ " data32 ljmp $0x10, $biosprotect\n"
+ "biosprotect: \n"
+ " .code32 \n"
+ " movw $0x18, %ax \n"
+ " mov %ax, %ds \n"
+ " mov %ax, %es \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+ " mov %ax, %ss \n"
+ " lidt idtarg \n"
+ " call biosint \n"
+ // back to real mode ...
+ " ljmp $0x28, $__rms_16bit2\n"
+ "__rms_16bit2: \n"
+ " .code16 \n"
+ /* 16 bit code from here on... */
+ /* Load the segment registers w/ properly configured segment
+ * descriptors. They will retain these configurations (limits,
+ * writability, etc.) once protected mode is turned off. */
+ " mov $0x30, %ax \n"
+ " mov %ax, %ds \n"
+ " mov %ax, %es \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+ " mov %ax, %ss \n"
+
+ /* Turn off protection (bit 0 in CR0) */
+ " movl %cr0, %eax \n"
+ " andl $0xFFFFFFFE, %eax \n"
+ " movl %eax, %cr0 \n"
+
+ /* Now really going into real mode */
+ " ljmp $0, $__rms_real2 \n"
+ "__rms_real2: \n"
+
+ /* Setup a stack
+ * FixME: where is esp? */
+ /* no need for a fix here. The esp is shared from 32-bit and 16-bit mode.
+ * you have to hack on the ss, but the esp remains the same across
+ * modes.
+ */
+ " mov $0x0, %ax \n"
+ " mov %ax, %ss \n"
+
+ /* debugging for RGM */
+ " mov $0x11, %al \n"
+ " outb %al, $0x80 \n"
+
+ /* Load our 16 bit idt */
+ " xor %ax, %ax \n"
+ " mov %ax, %ds \n"
+ " lidt __myidt \n"
+
+ /* Dump zeros in the other segregs */
+ " mov %ax, %es \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+ " mov $0x40, %ax \n"
+ " mov %ax, %ds \n"
+
+ /* pop the INT # that you pushed earlier */
+ " popl %eax \n"
+ " pop %gs \n"
+ " pop %fs \n"
+ " pop %es \n"
+ " pop %ds \n"
+ " popal \n"
+ " iret \n"
+ " .code32 \n"
+ );
+}
+
+enum {
+ PCIBIOS = 0x1a,
+ MEMSIZE = 0x12
+};
+
+int pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
+ unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
+ unsigned long *pecx, unsigned long *peax, unsigned long *pflags);
+
+int handleint21(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
+ unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
+ unsigned long *pecx, unsigned long *peax, unsigned long *pflags
+ );
+
+int biosint(unsigned long intnumber,
+ unsigned long gsfs, unsigned long dses,
+ unsigned long edi, unsigned long esi,
+ unsigned long ebp, unsigned long esp,
+ unsigned long ebx, unsigned long edx,
+ unsigned long ecx, unsigned long eax,
+ unsigned long cs_ip, unsigned short stackflags)
+{
+ unsigned long ip;
+ unsigned long cs;
+ unsigned long flags;
+ int ret = -1;
+
+ ip = cs_ip & 0xffff;
+ cs = cs_ip >> 16;
+ flags = stackflags;
+
+ printk_debug("biosint: INT# 0x%lx\n", intnumber);
+ printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
+ eax, ebx, ecx, edx);
+ printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+ ebp, esp, edi, esi);
+ printk_debug("biosint: ip 0x%x cs 0x%x flags 0x%x\n",
+ ip, cs, flags);
+ printk_debug("biosint: gs 0x%x fs 0x%x ds 0x%x es 0x%x\n",
+ gsfs >> 16, gsfs & 0xffff, dses >> 16, dses & 0xffff);
+
+ // cases in a good compiler are just as good as your own tables.
+ switch (intnumber) {
+ case 0 ... 15:
+ // These are not BIOS service, but the CPU-generated exceptions
+ printk_info("biosint: Oops, exception %u\n", intnumber);
+ if (esp < 0x1000) {
+ printk_debug("Stack contents: ");
+ while (esp < 0x1000) {
+ printk_debug("0x%04x ", *(unsigned short *) esp);
+ esp += 2;
+ }
+ printk_debug("\n");
+ }
+ printk_debug("biosint: Bailing out ... not now\n");
+ // "longjmp"
+ //vga_exit();
+ break;
+
+ case PCIBIOS:
+ ret = pcibios( &edi, &esi, &ebp, &esp,
+ &ebx, &edx, &ecx, &eax, &flags);
+ break;
+ case MEMSIZE:
+ // who cares.
+ eax = 64 * 1024;
+ ret = 0;
+ break;
+ case 0x15:
+ ret=handleint21( &edi, &esi, &ebp, &esp,
+ &ebx, &edx, &ecx, &eax, &flags);
+ break;
+ default:
+ printk_info("BIOSINT: Unsupport int #0x%x\n",
+ intnumber);
+ break;
+ }
+ if (ret)
+ flags |= 1; // carry flags
+ else
+ flags &= ~1;
+ stackflags = flags;
+ return ret;
+}
+
+
+void setup_realmode_idt(void)
+{
+ extern unsigned char idthandle, end_idthandle;
+ extern unsigned char debughandle, end_debughandle;
+
+ int i;
+ struct realidt *idts = (struct realidt *) 0;
+ int codesize = &end_idthandle - &idthandle;
+ unsigned char *intbyte, *codeptr;
+
+ // for each int, we create a customized little handler
+ // that just pushes %ax, puts the int # in %al,
+ // then calls the common interrupt handler.
+ // this necessitated because intel didn't know much about
+ // architecture when they did the 8086 (it shows)
+ // (hmm do they know anymore even now :-)
+ // obviously you can see I don't really care about memory
+ // efficiency. If I did I would probe back through the stack
+ // and get it that way. But that's really disgusting.
+ for (i = 0; i < 256; i++) {
+ idts[i].cs = 0;
+ codeptr = (char*) 4096 + i * codesize;
+ idts[i].offset = (unsigned) codeptr;
+ memcpy(codeptr, &idthandle, codesize);
+ intbyte = codeptr + 3;
+ *intbyte = i;
+ }
+
+ // fixed entry points
+
+ // VGA BIOSes tend to hardcode f000:f065 as the previous handler of
+ // int10.
+ // calling convention here is the same as INTs, we can reuse
+ // the int entry code.
+ codeptr = (char*) 0xff065;
+ memcpy(codeptr, &idthandle, codesize);
+ intbyte = codeptr + 3;
+ *intbyte = 0x42; /* int42 is the relocated int10 */
+
+ /* debug handler - useful to set a programmable delay between instructions if the
+ TF bit is set upon call to real mode */
+ idts[1].cs = 0;
+ idts[1].offset = 16384;
+ memcpy(16384, &debughandle, &end_debughandle - &debughandle);
+}
+
+
+
+enum {
+ CHECK = 0xb001,
+ FINDDEV = 0xb102,
+ READCONFBYTE = 0xb108,
+ READCONFWORD = 0xb109,
+ READCONFDWORD = 0xb10a,
+ WRITECONFBYTE = 0xb10b,
+ WRITECONFWORD = 0xb10c,
+ WRITECONFDWORD = 0xb10d
+};
+
+// errors go in AH. Just set these up so that word assigns
+// will work. KISS.
+enum {
+ PCIBIOS_NODEV = 0x8600,
+ PCIBIOS_BADREG = 0x8700
+};
+
+int
+pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
+ unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
+ unsigned long *pecx, unsigned long *peax, unsigned long *pflags)
+{
+ unsigned long edi = *pedi;
+ unsigned long esi = *pesi;
+ unsigned long ebp = *pebp;
+ unsigned long esp = *pesp;
+ unsigned long ebx = *pebx;
+ unsigned long edx = *pedx;
+ unsigned long ecx = *pecx;
+ unsigned long eax = *peax;
+ unsigned long flags = *pflags;
+ unsigned short func = (unsigned short) eax;
+ int retval = 0;
+ unsigned short devid, vendorid, devfn;
+ short devindex; /* Use short to get rid of gabage in upper half of 32-bit register */
+ unsigned char bus;
+ device_t dev;
+
+ switch(func) {
+ case CHECK:
+ *pedx = 0x4350;
+ *pecx = 0x2049;
+ retval = 0;
+ break;
+ case FINDDEV:
+ {
+ devid = *pecx;
+ vendorid = *pedx;
+ devindex = *pesi;
+ dev = 0;
+ while ((dev = dev_find_device(vendorid, devid, dev))) {
+ if (devindex <= 0)
+ break;
+ devindex--;
+ }
+ if (dev) {
+ unsigned short busdevfn;
+ *peax = 0;
+ // busnum is an unsigned char;
+ // devfn is an int, so we mask it off.
+ busdevfn = (dev->bus->secondary << 8)
+ | (dev->path.u.pci.devfn & 0xff);
+ printk_debug("0x%x: return 0x%x\n", func, busdevfn);
+ *pebx = busdevfn;
+ retval = 0;
+ } else {
+ *peax = PCIBIOS_NODEV;
+ retval = -1;
+ }
+ }
+ break;
+ case READCONFDWORD:
+ case READCONFWORD:
+ case READCONFBYTE:
+ case WRITECONFDWORD:
+ case WRITECONFWORD:
+ case WRITECONFBYTE:
+ {
+ unsigned long dword;
+ unsigned short word;
+ unsigned char byte;
+ unsigned char reg;
+
+ devfn = *pebx & 0xff;
+ bus = *pebx >> 8;
+ reg = *pedi;
+ dev = dev_find_slot(bus, devfn);
+ if (! dev) {
+ printk_debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
+ // idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
+ *peax = PCIBIOS_BADREG;
+ retval = -1;
+ }
+ switch(func) {
+ case READCONFBYTE:
+ byte = pci_read_config8(dev, reg);
+ *pecx = byte;
+ break;
+ case READCONFWORD:
+ word = pci_read_config16(dev, reg);
+ *pecx = word;
+ break;
+ case READCONFDWORD:
+ dword = pci_read_config32(dev, reg);
+ *pecx = dword;
+ break;
+ case WRITECONFBYTE:
+ byte = *pecx;
+ pci_write_config8(dev, reg, byte);
+ break;
+ case WRITECONFWORD:
+ word = *pecx;
+ pci_write_config16(dev, reg, word);
+ break;
+ case WRITECONFDWORD:
+ dword = *pecx;
+ pci_write_config32(dev, reg, dword);
+ break;
+ }
+
+ if (retval)
+ retval = PCIBIOS_BADREG;
+ printk_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+ func, bus, devfn, reg, *pecx);
+ *peax = 0;
+ retval = 0;
+ }
+ break;
+ default:
+ printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
+ break;
+ }
+
+ return retval;
+}
+
+int handleint21(unsigned long *edi, unsigned long *esi, unsigned long *ebp,
+ unsigned long *esp, unsigned long *ebx, unsigned long *edx,
+ unsigned long *ecx, unsigned long *eax, unsigned long *flags)
+{
+ int res=-1;
+ printk_debug("handleint21, eax 0x%x\n", *eax);
+ switch(*eax&0xffff)
+ {
+ case 0x5f19:
+ break;
+ case 0x5f18:
+ *eax=0x5f;
+ *ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory
+ *ecx=0x060;
+ res=0;
+ break;
+ case 0x5f00:
+ *eax = 0x8600;
+ break;
+ case 0x5f01:
+ *eax = 0x5f;
+ *ecx = (*ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768
+ res = 0;
+ break;
+ case 0x5f02:
+ *eax=0x5f;
+ *ebx= (*ebx & 0xffff0000) | 2;
+ *ecx= (*ecx & 0xffff0000) | 0x401; // PAL + crt only
+ *edx= (*edx & 0xffff0000) | 0; // TV Layout - default
+ res=0;
+ break;
+ case 0x5f0f:
+ *eax=0x860f;
+ break;
+ case 0xBEA7:
+ *eax=33;
+ break;
+ case 0xBEA4:
+ *eax=333;
+ break;
+ }
+ return res;
+}