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| author | Eric Biederman <ebiederm@xmission.com> | 2004-10-14 19:29:29 +0000 |
|---|---|---|
| committer | Eric Biederman <ebiederm@xmission.com> | 2004-10-14 19:29:29 +0000 |
| commit | fcd5ace00b333ce31b11b02a2243dfbf39307f10 (patch) | |
| tree | d686d752ccea9b185b0008c70d8523749b26e2dd /src/cpu/amd/mtrr/amd_earlymtrr.c | |
| parent | 98e619b1cefcb9871185f4cc3db85fa430dcdbce (diff) | |
| download | coreboot-fcd5ace00b333ce31b11b02a2243dfbf39307f10.tar.xz | |
- Add new cvs code to cvs
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/mtrr/amd_earlymtrr.c')
| -rw-r--r-- | src/cpu/amd/mtrr/amd_earlymtrr.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/cpu/amd/mtrr/amd_earlymtrr.c b/src/cpu/amd/mtrr/amd_earlymtrr.c new file mode 100644 index 0000000000..ca19a57faa --- /dev/null +++ b/src/cpu/amd/mtrr/amd_earlymtrr.c @@ -0,0 +1,46 @@ +#ifndef AMD_EARLYMTRR_C +#define AMD_EARLYMTRR_C +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> +#include "cpu/x86/mtrr/earlymtrr.c" + + +static void amd_early_mtrr_init(void) +{ + static const unsigned long mtrr_msrs[] = { + /* fixed mtrr */ + 0x250, 0x258, 0x259, + 0x268, 0x269, 0x26A, + 0x26B, 0x26C, 0x26D, + 0x26E, 0x26F, + /* var mtrr */ + 0x200, 0x201, 0x202, 0x203, + 0x204, 0x205, 0x206, 0x207, + 0x208, 0x209, 0x20A, 0x20B, + 0x20C, 0x20D, 0x20E, 0x20F, + /* var iorr */ + 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019, + /* mem top */ + 0xC001001A, 0xC001001D, + /* NULL end of table */ + 0 + }; + msr_t msr; + + disable_cache(); + do_early_mtrr_init(mtrr_msrs); + + /* Enable memory access for 0 - 1MB using top_mem */ + msr.hi = 0; + msr.lo = (((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK); + wrmsr(TOP_MEM, msr); + + /* Enable the MTRRs in SYSCFG */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrVarDramEn; + wrmsr(SYSCFG_MSR, msr); + + enable_cache(); +} + +#endif /* AMD_EARLYMTRR_C */ |