diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/cpu/amd/pi/00630F01 | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
| download | coreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.xz | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/cpu/amd/pi/00630F01')
| -rw-r--r-- | src/cpu/amd/pi/00630F01/fixme.c | 4 | ||||
| -rw-r--r-- | src/cpu/amd/pi/00630F01/model_15_init.c | 18 | ||||
| -rw-r--r-- | src/cpu/amd/pi/00630F01/udelay.c | 5 |
3 files changed, 14 insertions, 13 deletions
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 91450338aa..4feb1881cd 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -14,8 +14,8 @@ */ #include <cpu/x86/mtrr.h> +#include <cpu/amd/msr.h> #include <northbridge/amd/agesa/agesa_helper.h> - #include <Porting.h> #include <AGESA.h> #include <amdlib.h> @@ -79,7 +79,7 @@ void amd_initmmio(void) */ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 0269a1e260..503d5314ff 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -15,8 +15,10 @@ #include <console/console.h> #include <cpu/x86/msr.h> -#include <cpu/x86/smm.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> +#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <string.h> @@ -25,8 +27,6 @@ #include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/amdfam15.h> #include <arch/acpi.h> static void model_15_init(struct device *dev) @@ -70,12 +70,12 @@ static void model_15_init(struct device *dev) x86_enable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(MCG_CAP); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ setup_lapic(); @@ -105,14 +105,14 @@ static void model_15_init(struct device *dev) printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); /* Set SMM base address for this CPU */ - msr = rdmsr(MSR_SMM_BASE); + msr = rdmsr(SMM_BASE_MSR); msr.lo = SMM_BASE - (cpu_idx * 0x400); - wrmsr(MSR_SMM_BASE, msr); + wrmsr(SMM_BASE_MSR, msr); /* Enable the SMM memory window */ - msr = rdmsr(MSR_SMM_MASK); + msr = rdmsr(SMM_MASK_MSR); msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ - wrmsr(MSR_SMM_MASK, msr); + wrmsr(SMM_MASK_MSR, msr); } /* Write protect SMM space with SMMLOCK. */ diff --git a/src/cpu/amd/pi/00630F01/udelay.c b/src/cpu/amd/pi/00630F01/udelay.c index 5b08bedb1e..2cb53e9c20 100644 --- a/src/cpu/amd/pi/00630F01/udelay.c +++ b/src/cpu/amd/pi/00630F01/udelay.c @@ -21,6 +21,7 @@ */ #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> #include <cpu/x86/tsc.h> #include <delay.h> #include <stdint.h> @@ -36,11 +37,11 @@ void udelay(uint32_t us) tsc_start = rdtscll(); /* Get the P-state. This determines which MSR to read */ - msr = rdmsr(0xc0010063); + msr = rdmsr(PS_STS_REG); pstate_idx = msr.lo & 0x07; /* Get FID and VID for current P-State */ - msr = rdmsr(0xc0010064 + pstate_idx); + msr = rdmsr(PSTATE_0_MSR + pstate_idx); /* Extract the FID and VID values */ fid = msr.lo & 0x3f; |