summaryrefslogtreecommitdiff
path: root/src/cpu/amd/pi
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2017-06-27 22:54:42 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2017-06-28 00:23:32 +0000
commit168ef399c43ad79a40a8bbb2de921a2bd906b3f5 (patch)
tree16613245bebd7920cf3e7ce41f0d7bb5441f05e2 /src/cpu/amd/pi
parent70083a1de9e12d8dbd3ba70e7a36a7282090f0e0 (diff)
downloadcoreboot-168ef399c43ad79a40a8bbb2de921a2bd906b3f5.tar.xz
cpu/*: Add whitespace around '<<'
Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd/pi')
-rw-r--r--src/cpu/amd/pi/cache_as_ram.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc
index c0a69ec74a..55480070c9 100644
--- a/src/cpu/amd/pi/cache_as_ram.inc
+++ b/src/cpu/amd/pi/cache_as_ram.inc
@@ -43,7 +43,7 @@ cache_as_ram_setup:
/* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
movl %cr4, %eax
- orl $(3<<9), %eax
+ orl $(3 << 9), %eax
movl %eax, %cr4
/* Get the cpu_init_detected */