cpu/amd: Use common AMD's MSR

Phase 1. Due to the size of the effort, this CL is broken into several
phases.

Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>

7 files changed, 26 insertions, 25 deletions

diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
index 91450338aa..4feb1881cd 100644
--- a/src/cpu/amd/pi/00630F01/fixme.c
+++ b/src/cpu/amd/pi/00630F01/fixme.c
@@ -14,8 +14,8 @@
  */
 
 #include <cpu/x86/mtrr.h>
+#include <cpu/amd/msr.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
-
 #include <Porting.h>
 #include <AGESA.h>
 #include <amdlib.h>
@@ -79,7 +79,7 @@ void amd_initmmio(void)
 	 */
 	MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
 		(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
+	LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
index 0269a1e260..503d5314ff 100644
--- a/src/cpu/amd/pi/00630F01/model_15_init.c
+++ b/src/cpu/amd/pi/00630F01/model_15_init.c
@@ -15,8 +15,10 @@
 
 #include <console/console.h>
 #include <cpu/x86/msr.h>
-#include <cpu/x86/smm.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <string.h>
@@ -25,8 +27,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>
 
 static void model_15_init(struct device *dev)
@@ -70,12 +70,12 @@ static void model_15_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
-	msr = rdmsr(MCG_CAP);
+	msr = rdmsr(IA32_MCG_CAP);
 	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
 	for (i = 0; i < num_banks; i++)
-		wrmsr(MC0_STATUS + (i * 4), msr);
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
 
 	/* Enable the local CPU APICs */
 	setup_lapic();
@@ -105,14 +105,14 @@ static void model_15_init(struct device *dev)
 		printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
 
 		/* Set SMM base address for this CPU */
-		msr = rdmsr(MSR_SMM_BASE);
+		msr = rdmsr(SMM_BASE_MSR);
 		msr.lo = SMM_BASE - (cpu_idx * 0x400);
-		wrmsr(MSR_SMM_BASE, msr);
+		wrmsr(SMM_BASE_MSR, msr);
 
 		/* Enable the SMM memory window */
-		msr = rdmsr(MSR_SMM_MASK);
+		msr = rdmsr(SMM_MASK_MSR);
 		msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
-		wrmsr(MSR_SMM_MASK, msr);
+		wrmsr(SMM_MASK_MSR, msr);
 	}
 
 	/* Write protect SMM space with SMMLOCK. */
diff --git a/src/cpu/amd/pi/00630F01/udelay.c b/src/cpu/amd/pi/00630F01/udelay.c
index 5b08bedb1e..2cb53e9c20 100644
--- a/src/cpu/amd/pi/00630F01/udelay.c
+++ b/src/cpu/amd/pi/00630F01/udelay.c
@@ -21,6 +21,7 @@
  */
 
 #include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
 #include <cpu/x86/tsc.h>
 #include <delay.h>
 #include <stdint.h>
@@ -36,11 +37,11 @@ void udelay(uint32_t us)
 	tsc_start = rdtscll();
 
 	/* Get the P-state. This determines which MSR to read */
-	msr = rdmsr(0xc0010063);
+	msr = rdmsr(PS_STS_REG);
 	pstate_idx = msr.lo & 0x07;
 
 	/* Get FID and VID for current P-State */
-	msr = rdmsr(0xc0010064 + pstate_idx);
+	msr = rdmsr(PSTATE_0_MSR + pstate_idx);
 
 	/* Extract the FID and VID values */
 	fid = msr.lo & 0x3f;
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
index a4c574ced7..0bad4679ce 100644
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ b/src/cpu/amd/pi/00660F01/fixme.c
@@ -14,8 +14,8 @@
  */
 
 #include <cpu/x86/mtrr.h>
+#include <cpu/amd/msr.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
-
 #include <Porting.h>
 #include <AGESA.h>
 #include <amdlib.h>
@@ -80,7 +80,7 @@ void amd_initmmio(void)
 	 */
 	MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
 		(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
+	LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
 
 	/* For serial port */
 	PciData = 0xFF03FFD5;
diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
index 424a6c06ff..3f3a1fda44 100644
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ b/src/cpu/amd/pi/00660F01/model_15_init.c
@@ -15,6 +15,8 @@
 
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -24,8 +26,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>
 
 #include <amdlib.h>
@@ -82,12 +82,12 @@ static void model_15_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
-	msr = rdmsr(MCG_CAP);
+	msr = rdmsr(IA32_MCG_CAP);
 	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
 	for (i = 0; i < num_banks; i++)
-		wrmsr(MC0_STATUS + (i * 4), msr);
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
 
 	/* Enable the local CPU APICs */
 	setup_lapic();
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c
index f6334a8a78..9f4c5289bb 100644
--- a/src/cpu/amd/pi/00730F01/fixme.c
+++ b/src/cpu/amd/pi/00730F01/fixme.c
@@ -14,8 +14,8 @@
  */
 
 #include <cpu/x86/mtrr.h>
+#include <cpu/amd/msr.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
-
 #include <Porting.h>
 #include <AGESA.h>
 #include <amdlib.h>
@@ -80,7 +80,7 @@ void amd_initmmio(void)
 	 */
 	MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
 		(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
+	LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
 
 	/* For serial port */
 	PciData = 0xFF03FFD5;
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 1f2c30fd03..f5121d1a4f 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -15,6 +15,8 @@
 
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -24,8 +26,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/amdfam16.h>
 #include <arch/acpi.h>
 
 static void model_16_init(struct device *dev)
@@ -67,12 +67,12 @@ static void model_16_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
-	msr = rdmsr(MCG_CAP);
+	msr = rdmsr(IA32_MCG_CAP);
 	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
 	for (i = 0; i < num_banks; i++)
-		wrmsr(MC0_STATUS + (i * 4), msr);
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
 
 	/* Enable the local CPU APICs */
 	setup_lapic();