AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK

Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 0 insertions, 82 deletions

diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
index d94215a44b..4699eeac26 100644
--- a/src/cpu/amd/pi/00630F01/fixme.c
+++ b/src/cpu/amd/pi/00630F01/fixme.c
@@ -65,24 +65,3 @@ void amd_initcpuio(void)
 	PciData = 0x00000003;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 }
-
-void amd_initmmio(void)
-{
-	UINT64                        MsrReg;
-	AMD_CONFIG_PARAMS             StdHeader;
-
-	/*
-	 * Set the MMIO Configuration Base Address
-	 * and Bus Range onto MMIO configuration base
-	 * Address MSR register.
-	 */
-	MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
-		(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
-
-	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
-	LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
-	LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
-}
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
index 7d71e2ea1a..1ce7432fe4 100644
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ b/src/cpu/amd/pi/00660F01/fixme.c
@@ -64,31 +64,3 @@ void amd_initcpuio(void)
 	PciData = 0x00000003;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 }
-
-void amd_initmmio(void)
-{
-	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
-	AMD_CONFIG_PARAMS             StdHeader;
-
-	/*
-	 * Set the MMIO Configuration Base Address and
-	 * Bus Range onto MMIO configuration base
-	 * Address MSR register.
-	 */
-	MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
-		(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
-
-	/* For serial port */
-	PciData = 0xFF03FFD5;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
-	LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
-	LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
-}
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c
index 7edd1b8fa2..1ce7432fe4 100644
--- a/src/cpu/amd/pi/00730F01/fixme.c
+++ b/src/cpu/amd/pi/00730F01/fixme.c
@@ -64,36 +64,3 @@ void amd_initcpuio(void)
 	PciData = 0x00000003;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 }
-
-void amd_initmmio(void)
-{
-	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
-	AMD_CONFIG_PARAMS             StdHeader;
-
-	/*
-	 * Set the MMIO Configuration Base Address and
-	 * Bus Range onto MMIO configuration base
-	 * Address MSR register.
-	 */
-	MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
-		(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
-
-	/* For serial port */
-	PciData = 0xFF03FFD5;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* PSP */
-	//PciData = 0xD;
-	//PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x8, 0x0, 0x48);
-	//LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
-	LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
-	LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
-}