diff options
| author | Arne Georg Gleditsch <arne.gleditsch@numascale.com> | 2010-03-10 03:43:05 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2010-03-10 03:43:05 +0000 |
| commit | bc259d09d342f09987c65290422009615a8287a7 (patch) | |
| tree | d196eca916b402b6875c668ed18fb99ec7c9bac5 /src/cpu/amd/quadcore | |
| parent | a51021b9a11ab0910fb3fa827c0dd094a89960bb (diff) | |
| download | coreboot-bc259d09d342f09987c65290422009615a8287a7.tar.xz | |
The following patch implements Opteron Fam 10 rev D (aka Istanbul)
support for coreboot. I have not updated MAX_CPUS for all fam10
mainboards, but it might make sense to multiply those by 1.5.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
I assume the line
pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword);
should be put outside the loop.
Everything seems to be fine. I don't have Istanbul to test. I have
read every changes and they all look good.
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/quadcore')
| -rw-r--r-- | src/cpu/amd/quadcore/quadcore.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index ac62981723..7d621c5375 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -29,7 +29,11 @@ static u32 get_core_num_in_bsp(u32 nodeid) u32 dword; dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8); dword >>= 12; - dword &= 3; + /* Bit 15 is CmpCap[2] since Revision D. */ + if ((cpuid_ecx(0x80000008) & 0xff) > 3) + dword = ((dword & 8) >> 1) | (dword & 3); + else + dword &= 3; return dword; } @@ -53,7 +57,7 @@ static void set_apicid_cpuid_lo(void) { } static void real_start_other_core(u32 nodeid, u32 cores) { - u32 dword; + u32 dword, i; printk_debug("Start other core - nodeid: %02x cores: %02x\n", nodeid, cores); @@ -69,9 +73,8 @@ static void real_start_other_core(u32 nodeid, u32 cores) if(cores > 1) { dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168); - dword |= (1 << 0); // core2 - if(cores > 2) { // core3 - dword |= (1 << 1); + for (i = 0; i < cores - 1; i++) { + dword |= 1 << i; } pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword); } |