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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-23 21:07:28 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-28 18:47:23 +0200 |
| commit | cbe7464c623d148c96974f0ce8724ead0ad5478d (patch) | |
| tree | e47ead759132c68dbbd5a498184c3ef2c46f8b75 /src/cpu/amd/quadcore | |
| parent | 3f4aece4e07b15a5a2d191873da04b88c8e87049 (diff) | |
| download | coreboot-cbe7464c623d148c96974f0ce8724ead0ad5478d.tar.xz | |
src/cpu: Add required space before opening parenthesis '('
Change-Id: I7fb9bfcaeec0b9dfd0695d2b2d398fd01091f6bc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16286
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
Diffstat (limited to 'src/cpu/amd/quadcore')
| -rw-r--r-- | src/cpu/amd/quadcore/amd_sibling.c | 12 | ||||
| -rw-r--r-- | src/cpu/amd/quadcore/quadcore_id.c | 2 |
2 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index ec5744bdce..c4eb50cd2c 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -41,11 +41,11 @@ static u32 get_max_siblings(u32 nodes) u32 siblings=0; //get max siblings from all the nodes - for(nodeid=0; nodeid<nodes; nodeid++){ + for (nodeid=0; nodeid<nodes; nodeid++){ int j; dev = get_node_pci(nodeid, 3); j = (pci_read_config32(dev, 0xe8) >> 12) & 3; - if(siblings < j) { + if (siblings < j) { siblings = j; } } @@ -60,7 +60,7 @@ static void enable_apic_ext_id(u32 nodes) u32 nodeid; //enable APIC_EXIT_ID all the nodes - for(nodeid=0; nodeid<nodes; nodeid++){ + for (nodeid=0; nodeid<nodes; nodeid++){ u32 val; dev = get_node_pci(nodeid, 0); val = pci_read_config32(dev, 0x68); @@ -82,7 +82,7 @@ u32 get_apicid_base(u32 ioapic_num) siblings = get_max_siblings(sysconf.nodes); - if(sysconf.bsp_apicid > 0) { // IOAPIC could start from 0 + if (sysconf.bsp_apicid > 0) { // IOAPIC could start from 0 return 0; } else if (sysconf.enabled_apic_ext_id) { // enabled ext id but bsp = 0 return 1; @@ -93,7 +93,7 @@ u32 get_apicid_base(u32 ioapic_num) //Construct apicid_base - if((!disable_siblings) && (siblings>0) ) { + if ((!disable_siblings) && (siblings>0) ) { /* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel and the kernel will try to get one that is small than 16 to make IOAPIC work. I don't @@ -108,7 +108,7 @@ u32 get_apicid_base(u32 ioapic_num) apicid_base = sysconf.nodes; } - if((apicid_base+ioapic_num-1)>0xf) { + if ((apicid_base+ioapic_num-1)>0xf) { // We need to enable APIC EXT ID printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n"); enable_apic_ext_id(sysconf.nodes); diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index b89aac7e65..cd83906f0e 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -75,7 +75,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54) * The apicid format varies based on processor revision */ apicid = (cpuid_ebx(1) >> 24) & 0xff; - if( nb_cfg_54) { + if ( nb_cfg_54) { if (fam15h && dual_node) { id.coreid = apicid & 0x1f; id.nodeid = (apicid & 0x60) >> 5; |