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authorAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-09-30 20:23:09 -0700
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-10-15 03:52:49 +0000
commit86091f94b6ca58f4b8795503b274492d6a935c15 (patch)
treedb6e5f77dc57850b25574aed5063743ca4bc4d48 /src/cpu/amd/smm
parent58562405c8c416a415652516b8af31b204b4ff0d (diff)
downloadcoreboot-86091f94b6ca58f4b8795503b274492d6a935c15.tar.xz
cpu/mtrr.h: Fix macro names for MTRR registers
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR, we also remove the _MSR suffix, as they are, by definition, MSRs. Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11761 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/amd/smm')
-rw-r--r--src/cpu/amd/smm/smm_init.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c
index 2e9a4c9ba3..e13f24f03a 100644
--- a/src/cpu/amd/smm/smm_init.c
+++ b/src/cpu/amd/smm/smm_init.c
@@ -39,7 +39,7 @@ void smm_init(void)
/* Back up MSRs for later restore */
syscfg_orig = rdmsr(SYSCFG_MSR);
- mtrr_aseg_orig = rdmsr(MTRRfix16K_A0000_MSR);
+ mtrr_aseg_orig = rdmsr(MTRR_FIX_16K_A0000);
/* MTRR changes don't like an enabled cache */
disable_cache();
@@ -57,7 +57,7 @@ void smm_init(void)
/* set DRAM access to 0xa0000 */
msr.lo = 0x18181818;
msr.hi = 0x18181818;
- wrmsr(MTRRfix16K_A0000_MSR, msr);
+ wrmsr(MTRR_FIX_16K_A0000, msr);
/* enable the extended features */
msr = syscfg_orig;
@@ -73,7 +73,7 @@ void smm_init(void)
/* Restore SYSCFG and MTRR */
wrmsr(SYSCFG_MSR, syscfg_orig);
- wrmsr(MTRRfix16K_A0000_MSR, mtrr_aseg_orig);
+ wrmsr(MTRR_FIX_16K_A0000, mtrr_aseg_orig);
enable_cache();
/* CPU MSR are set in CPU init */