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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-07-07 11:30:48 +0300
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 23:14:28 +0200
commit8b95c134207de9573f8e5eb758e5cee51741604a (patch)
tree8d49f7f9ce75bf9f0ae9ba26883588753e764f00 /src/cpu/amd/socket_C32
parent3ad5a9b97f2d66764880e0cf01b1833d39ddd5ce (diff)
downloadcoreboot-8b95c134207de9573f8e5eb758e5cee51741604a.tar.xz
AMD: Kconfig cleanup
Change-Id: Ie347b32575c26133d52c275622d29d1cd4c6c0c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3623 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/cpu/amd/socket_C32')
-rw-r--r--src/cpu/amd/socket_C32/Kconfig9
1 files changed, 3 insertions, 6 deletions
diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig
index f8e441f1e7..97b37ee814 100644
--- a/src/cpu/amd/socket_C32/Kconfig
+++ b/src/cpu/amd/socket_C32/Kconfig
@@ -6,33 +6,30 @@ config CPU_AMD_SOCKET_C32_NON_AGESA
select CACHE_AS_RAM
select X86_AMD_FIXED_MTRRS
+if CPU_AMD_SOCKET_C32_NON_AGESA
+
config CPU_SOCKET_TYPE
hex
default 0x14
- depends on CPU_AMD_SOCKET_C32_NON_AGESA
config EXT_RT_TBL_SUPPORT
bool
default n
- depends on CPU_AMD_SOCKET_C32_NON_AGESA
config EXT_CONF_SUPPORT
bool
default n
- depends on CPU_AMD_SOCKET_C32_NON_AGESA
config CBB
hex
default 0x0
- depends on CPU_AMD_SOCKET_C32_NON_AGESA
config CDB
hex
default 0x18
- depends on CPU_AMD_SOCKET_C32_NON_AGESA
config XIP_ROM_SIZE
hex
default 0x80000
- depends on CPU_AMD_SOCKET_C32_NON_AGESA
+endif