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| author | Siyuan Wang <wangsiyuanbuaa@gmail.com> | 2012-09-07 18:35:17 +0800 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2012-09-19 23:15:27 +0200 |
| commit | 1fb49dfa5ea50475da501168717fc8c53e918075 (patch) | |
| tree | 095aacdc29317b48e41263e380c6803248bd7303 /src/cpu/amd/socket_C32 | |
| parent | fec5b647fc05484f8d8703f118f84e958b85329e (diff) | |
| download | coreboot-1fb49dfa5ea50475da501168717fc8c53e918075.tar.xz | |
C32 legacy code: change CONFIG_CPU_AMD_SOCKET_C32 to CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA
Currently the C32 has some legacy boards which use the old C32 code. We need to seperate them.
CONFIG_CPU_AMD_SOCKET_C32 was used in legacy code before.
But it is not a good idea, so we change the code as follows:
So we use CONFIG_CPU_AMD_SOCKET_C32 to identify mainboard which uses agesa code,
and use CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA to identify mainboard which uses legacy code.
Change-Id: If6114bf8912e78b7732f25a1adfb2e4d8eb10ee4
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1497
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/cpu/amd/socket_C32')
| -rw-r--r-- | src/cpu/amd/socket_C32/Kconfig | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig index 56324dc776..db4b624c15 100644 --- a/src/cpu/amd/socket_C32/Kconfig +++ b/src/cpu/amd/socket_C32/Kconfig @@ -1,4 +1,4 @@ -config CPU_AMD_SOCKET_C32 +config CPU_AMD_SOCKET_C32_NON_AGESA bool select CPU_AMD_MODEL_10XXX select HT3_SUPPORT @@ -8,30 +8,30 @@ config CPU_AMD_SOCKET_C32 config CPU_SOCKET_TYPE hex default 0x14 - depends on CPU_AMD_SOCKET_C32 + depends on CPU_AMD_SOCKET_C32_NON_AGESA config EXT_RT_TBL_SUPPORT bool default n - depends on CPU_AMD_SOCKET_C32 + depends on CPU_AMD_SOCKET_C32_NON_AGESA config EXT_CONF_SUPPORT bool default n - depends on CPU_AMD_SOCKET_C32 + depends on CPU_AMD_SOCKET_C32_NON_AGESA config CBB hex default 0x0 - depends on CPU_AMD_SOCKET_C32 + depends on CPU_AMD_SOCKET_C32_NON_AGESA config CDB hex default 0x18 - depends on CPU_AMD_SOCKET_C32 + depends on CPU_AMD_SOCKET_C32_NON_AGESA config XIP_ROM_SIZE hex default 0x80000 - depends on CPU_AMD_SOCKET_C32 + depends on CPU_AMD_SOCKET_C32_NON_AGESA |