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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-20 08:03:49 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-01 05:47:18 +0100
commit7d25651ed3eb78228a00b479454d0ab2417f3f2a (patch)
tree07c33833b4a763def10d3c7002439a04c1468f76 /src/cpu/amd
parent036a581b8fa9478d4dba1bf9e576ee9cc0bead24 (diff)
downloadcoreboot-7d25651ed3eb78228a00b479454d0ab2417f3f2a.tar.xz
AGESA f14: Consolidate early P-states setting
Change-Id: I3feed296b6ff9908e783c1221a8f61d9c548fef4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17564 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/amd')
-rw-r--r--src/cpu/amd/agesa/family14/fixme.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index ab10e3a704..25a32bdb9c 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -98,6 +98,10 @@ void amd_initmmio(void)
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+
+ /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */
+ MsrReg = 0;
+ LibAmdMsrWrite (0xC0010062, &MsrReg, &StdHeader);
}
void amd_initenv(void)