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authorElyes HAOUAS <ehaouas@noos.fr>2018-05-28 15:41:12 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-06-04 09:13:11 +0000
commit9d75957116d9c191771fa9f0f9c436813f938e01 (patch)
treedbc69ca087406af674e3d630d7b1801ab5d83c1f /src/cpu/amd
parent0d8f1dac9e505eb3b0c8c4b58c06398cf465fdc4 (diff)
downloadcoreboot-9d75957116d9c191771fa9f0f9c436813f938e01.tar.xz
src/cpu: Get rid of whitespace before tab
Change-Id: Ic501f5f9e8cd79774eb2a8d8902f01853d746470 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/amd')
-rw-r--r--src/cpu/amd/family_10h-family_15h/defaults.h36
-rw-r--r--src/cpu/amd/microcode/microcode.c6
2 files changed, 21 insertions, 21 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
index 88950a3314..50b3d07a0d 100644
--- a/src/cpu/amd/family_10h-family_15h/defaults.h
+++ b/src/cpu/amd/family_10h-family_15h/defaults.h
@@ -523,7 +523,7 @@ static const struct {
/* Errata 281 Workaround */
{ 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1),
AMD_PTYPE_SVR, 0x00000001, 0x0000000F },
- /* [3:0] RspTok = 0001b */
+ /* [3:0] RspTok = 0001b */
{ 3, 0x144, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000028, 0x000000ff },
@@ -758,7 +758,7 @@ static const struct {
0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
- 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
+ 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
/* Link Phy Receiver Loop Filter Registers */
{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
@@ -782,28 +782,28 @@ static const struct {
[20:16] RttIndex = 04h */
{ 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,
- P0XmtRdPtr = 0x2
- P1RcvRdPtr = 0xa
- P1XmtRdPtr = 0x0 */
+ 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,
+ P0XmtRdPtr = 0x2
+ P1RcvRdPtr = 0xa
+ P1XmtRdPtr = 0x0 */
{ 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,
- P0XmtRdPtr = 0x2
- P1RcvRdPtr = 0xa
- P1XmtRdPtr = 0x0 */
+ 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,
+ P0XmtRdPtr = 0x2
+ P1RcvRdPtr = 0xa
+ P1XmtRdPtr = 0x0 */
{ 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
- 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,
- P0XmtRdPtr = 0x4
- P1RcvRdPtr = 0xd
- P1XmtRdPtr = 0x0 */
+ 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,
+ P0XmtRdPtr = 0x4
+ P1RcvRdPtr = 0xd
+ P1XmtRdPtr = 0x0 */
{ 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
- 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,
- P0XmtRdPtr = 0x4
- P1RcvRdPtr = 0xd
- P1XmtRdPtr = 0x0 */
+ 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,
+ P0XmtRdPtr = 0x4
+ P1RcvRdPtr = 0xd
+ P1XmtRdPtr = 0x0 */
/* Link Phy Receiver Loop Filter Registers */
{ 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index 71ecc01a36..541d5a81aa 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -30,9 +30,9 @@
#define UCODE_SECTION_START_ID 0x00000001
#define UCODE_MAGIC 0x00414d44
-#define F1XH_MPB_MAX_SIZE 2048
-#define F15H_MPB_MAX_SIZE 4096
-#define CONT_HDR 12
+#define F1XH_MPB_MAX_SIZE 2048
+#define F15H_MPB_MAX_SIZE 4096
+#define CONT_HDR 12
#define SECT_HDR 8
/*