summaryrefslogtreecommitdiff
path: root/src/cpu/amd
diff options
context:
space:
mode:
authorRonald G. Minnich <rminnich@gmail.com>2006-06-10 22:57:15 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-06-10 22:57:15 +0000
commitfb937496428272c5bc9001d98fb99a70961f7df4 (patch)
treeb3185771903cc9c00fd38d87ab9f87698c2f42d3 /src/cpu/amd
parent890ee09a3224f1cfc832f7c8f03e6c2f076aeb20 (diff)
downloadcoreboot-fb937496428272c5bc9001d98fb99a70961f7df4.tar.xz
changes from AMD for making OLPC video work.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd')
-rw-r--r--src/cpu/amd/model_gx2/cpubug.c74
-rw-r--r--src/cpu/amd/model_gx2/cpureginit.c15
-rw-r--r--src/cpu/amd/model_gx2/vsmsetup.c7
3 files changed, 67 insertions, 29 deletions
diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/model_gx2/cpubug.c
index 3c51208938..e38bbfbaa3 100644
--- a/src/cpu/amd/model_gx2/cpubug.c
+++ b/src/cpu/amd/model_gx2/cpubug.c
@@ -31,25 +31,46 @@ bug573(void){
}
#endif
+/**************************************************************************
+ *
+ * pcideadlock
+ *
+ * Bugtool #465 and #609
+ * PCI cache deadlock
+ * There is also fix code in cache and PCI functions. This bug is very is pervasive.
+ *
+ * Entry:
+ * Exit:
+ * Modified:
+ *
+ **************************************************************************/
static void
pcideadlock(void)
{
msr_t msr;
+ /*
+ * forces serialization of all load misses. Setting this bit prevents the
+ * DM pipe from backing up if a read request has to be held up waiting
+ * for PCI writes to complete.
+ */
msr = rdmsr(CPU_DM_CONFIG0);
msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
wrmsr(CPU_DM_CONFIG0, msr);
+ /* interlock instruction fetches to WS regions with data accesses.
+ * This prevents an instruction fetch from going out to PCI if the
+ * data side is about to make a request.
+ */
msr = rdmsr(CPU_IM_CONFIG);
- msr.lo |= IM_CONFIG_LOWER_QWT_SET; /* interlock instruction fetches to WS regions with data accesses.
- * This prevents in instruction fetch from going out to PCI if the
- * data side is about to make a request.
- */
+ msr.lo |= IM_CONFIG_LOWER_QWT_SET;
wrmsr(CPU_IM_CONFIG, msr);
- /* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/
-
+
+ /* write serialize memory hole to PCI. Need to unWS when something is
+ * shadowed regardless of cachablility.
+ */
msr.lo = 0x021212121;
msr.hi = 0x021212121;
wrmsr( CPU_RCONF_A0_BF, msr);
@@ -57,18 +78,18 @@ pcideadlock(void)
wrmsr( CPU_RCONF_E0_FF, msr);
}
-/****************************************************************************/
-/***/
-/** CPUbug784*/
-/***/
-/** Bugtool #784 + #792*/
-/***/
-/** Fix CPUID instructions for < 3.0 CPUs*/
-/***/
-/** Entry:*/
-/** Exit:*/
-/** Modified:*/
-/***/
+/****************************************************************************
+ *
+ * CPUbug784
+ *
+ * Bugtool #784 + #792
+ *
+ * Fix CPUID instructions for < 3.0 CPUs
+ *
+ * Entry:
+ * Exit:
+ * Modified:
+ *
/****************************************************************************/
void bug784(void)
@@ -99,18 +120,31 @@ void bug784(void)
}
/* cpubug 1398: enable MC if we KNOW we have DDR*/
+/**************************************************************************
+ *
+ * CPUbugIAENG1398
+ *
+ * ClearQuest #IAENG1398
+ * The MC can not be enabled with SDR memory but can for DDR. Enable for
+ * DDR here if the setup token is "Default"
+ * Add this back to core by default once 2.0 CPUs are not supported.
+ * Entry:
+ * Exit:
+ * Modified:
+ *
+ **************************************************************************/
void eng1398(void)
{
msr_t msr;
msr = rdmsr(MSR_GLCP+0x17);
- if ((msr.lo & 0xff) < CPU_REV_2_0) {
+ if ((msr.lo & 0xff) <= CPU_REV_2_0) {
msr = rdmsr(GLCP_SYS_RSTPLL);
if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
return;
}
- /* no bios to check, we just go for it? */
+ /* no CMOS/NVRAM to check, so enable MC Clock Gating */
msr = rdmsr(MC_GLD_MSR_PM);
msr.lo |= 3; /* enable MC clock gating.*/
wrmsr(MC_GLD_MSR_PM, msr);
diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c
index f2802b67ca..779669c34a 100644
--- a/src/cpu/amd/model_gx2/cpureginit.c
+++ b/src/cpu/amd/model_gx2/cpureginit.c
@@ -24,8 +24,8 @@ BIST(void){
msrnum = CPU_DM_BIST;
wrmsr(msrnum, msr);
- outb(POST_CPU_DM_BIST_FAILURE , 0x80); /* 0x29*/
- msr = rdmsr(msrnum); /* read back for pass fail*/
+ outb(POST_CPU_DM_BIST_FAILURE, 0x80); /* 0x29*/
+ msr = rdmsr(msrnum); /* read back for pass fail*/
msr.lo &= 0x0F3FF0000;
if (msr.lo != 0xfeff0000)
goto BISTFail;
@@ -80,7 +80,10 @@ cpuRegInit (void){
msr_t msr;
/* Turn on BTM for early debug based on setup. */
/*if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) {*/
- {
+ /*
+ * The following is only for diagnostics mode; do not use for OLPC
+ */
+ if (0) {
/* Set Diagnostic Mode */
msrnum = CPU_GLD_MSR_DIAG;
msr.hi = 0;
@@ -91,7 +94,7 @@ cpuRegInit (void){
msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
msr.hi = 0x0;
msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
- wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
+ wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
/* ;Turn off debug clock*/
msrnum = 0x04C000016; /* DBG_CLK_CTL*/
@@ -108,8 +111,8 @@ cpuRegInit (void){
/* ;Set fifo ctl to BTM bits wide*/
msrnum = 0x04C00005E; /* FIFO_CTL*/
msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/
- wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/
- /* Bit [19] sets it up in slow data mode.*/
+ wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/
+ /* Bit [19] sets it up in slow data mode.*/
/* ;enable fifo loading - BTM sizing will constrain*/
/* ; only valid BTM packets to load - this action should always be on*/
diff --git a/src/cpu/amd/model_gx2/vsmsetup.c b/src/cpu/amd/model_gx2/vsmsetup.c
index cd734f6fdb..d6955e7f2f 100644
--- a/src/cpu/amd/model_gx2/vsmsetup.c
+++ b/src/cpu/amd/model_gx2/vsmsetup.c
@@ -5,6 +5,7 @@
#undef __KERNEL__
#include <arch/io.h>
#include <string.h>
+#include <cpu/amd/gx2def.h>
/* what a mess this uncompress thing is. I am not at all happy about how this
* was done, but can't fix it yet. RGM
@@ -335,7 +336,7 @@ void do_vsmbios(void)
unsigned long busdevfn;
unsigned int rom = 0;
unsigned char *buf;
- unsigned int size = 256*1024;
+ unsigned int size = SMM_SIZE*1024;
int i;
printk_err("do_vsmbios\n");
@@ -353,12 +354,12 @@ void do_vsmbios(void)
//rom = 0xfff80000;
//rom = 0xfffc0000;
/* the VSA starts at the base of rom - 64 */
- rom = ((unsigned long) 0) - (ROM_SIZE + 35*1024);
+ rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024);
buf = (unsigned char *) 0x60000;
unrv2b((uint8_t *)rom, buf);
printk_debug("buf %p *buf %d buf[256k] %d\n",
- buf, buf[0], buf[256*1024]);
+ buf, buf[0], buf[SMM_SIZE*1024]);
printk_debug("buf[0x20] signature is %x:%x:%x:%x\n",
buf[0x20] ,buf[0x21] ,buf[0x22],buf[0x23]);
/* check for post code at start of vsainit.bin. If you don't see it,