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| author | Mike Loptien <mike.loptien@se-eng.com> | 2013-07-17 15:14:59 -0600 |
|---|---|---|
| committer | Bruce Griffith <Bruce.Griffith@se-eng.com> | 2013-08-15 18:40:11 +0200 |
| commit | ac90d8013a26d99df21cb555bb313506ce32979c (patch) | |
| tree | 3d5eedc01f54116d49a9aa649d081020d73c8097 /src/cpu/amd | |
| parent | 81c70fb142326fe9e5ac5391cdd45f93c984e3e6 (diff) | |
| download | coreboot-ac90d8013a26d99df21cb555bb313506ce32979c.tar.xz | |
AMD Kabini: Split DSDT into common sections
Split the Family16 (Kabini) DSDT file into logical regions.
Olive Hill is the only mainboard and Kabini is the only NB/CPU
currently using Family16 AGESA code.
Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3821
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/amd')
| -rw-r--r-- | src/cpu/amd/agesa/family16kb/acpi/cpu.asl | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl new file mode 100644 index 0000000000..9d1a75bf4f --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Processor Object + * + */ +Scope (\_PR) { /* define processor scope */ + Processor( + P000, /* name space name */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + + Processor( + P001, /* name space name */ + 1, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P002, /* name space name */ + 2, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P003, /* name space name */ + 3, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P004, /* name space name */ + 4, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P005, /* name space name */ + 5, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P006, /* name space name */ + 6, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P007, /* name space name */ + 7, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } +} /* End _PR scope */ |