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| author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2011-02-27 23:56:00 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-02-27 23:56:00 +0000 |
| commit | d26e5e6bb3209f195ef9cacdda1b18525f30fa62 (patch) | |
| tree | b066037457a80b748bf28ebe800d95b5bda03d7d /src/cpu/amd | |
| parent | 40f9b4b07e98f35336458cdc7a9a6257fb842470 (diff) | |
| download | coreboot-d26e5e6bb3209f195ef9cacdda1b18525f30fa62.tar.xz | |
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid. Factor out a little common code.
Also, our earlier config_clk_power_ctrl_reg0
was still too long and it'd get longer with forthcoming patches.
We now take apart F3xD4[PowerStepUp,PowerStepDown]
to its own function.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd')
| -rw-r--r-- | src/cpu/amd/model_10xxx/fidvid.c | 48 |
1 files changed, 27 insertions, 21 deletions
diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index 7ce2aea193..2d704011b0 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -179,32 +179,16 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) pci_write_config32(dev, 0xd8, dtemp); } -static void config_clk_power_ctrl_reg0(int node) { - u32 dword; - device_t dev = NODE_PCI(node, 3); - /* Program fields in Clock Power/Control register0 (F3xD4) */ - - /* set F3xD4 Clock Power/Timing Control 0 Register - * NbClkDidApplyAll=1b - * NbClkDid=100b - * PowerStepUp= "platform dependent" - * PowerStepDown= "platform dependent" - * LinkPllLink=01b - * ClkRampHystSel=HW default - */ +static u32 power_up_down(int node) { + u32 dword=0; /* check platform type */ if (!(get_platform_type() & AMD_PTYPE_SVR)) { /* For non-server platform * PowerStepUp=01000b - 50nS * PowerStepDown=01000b - 50ns */ - dword = pci_read_config32(dev, 0xd4); - dword &= CPTC0_MASK; - dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 | LNK_PLL_LOCK; /* per BKDG */ - pci_write_config32(dev, 0xd4, dword); + dword |= PW_STP_UP50 | PW_STP_DN50 ; } else { - dword = pci_read_config32(dev, 0xd4); - dword &= CPTC0_MASK; /* get number of cores for PowerStepUp & PowerStepDown in server 1 core - 400nS - 0000b 2 cores - 200nS - 0010b @@ -226,9 +210,31 @@ static void config_clk_power_ctrl_reg0(int node) { dword |= PW_STP_UP100 | PW_STP_DN100; break; } - dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK; - pci_write_config32(dev, 0xd4, dword); } + return dword; +} + +static void config_clk_power_ctrl_reg0(int node) { + device_t dev = NODE_PCI(node, 3); + + + /* Program fields in Clock Power/Control register0 (F3xD4) */ + + /* set F3xD4 Clock Power/Timing Control 0 Register + * NbClkDidApplyAll=1b + * NbClkDid=100b + * PowerStepUp= "platform dependent" + * PowerStepDown= "platform dependent" + * LinkPllLink=01b + * ClkRampHystSel=HW default + */ + u32 dword= pci_read_config32(dev, 0xd4); + dword &= CPTC0_MASK; + dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK; /* per BKDG */ + dword |= power_up_down(node); + + pci_write_config32(dev, 0xd4, dword); + } static void config_power_ctrl_misc_reg(device_t dev) { |