cpu/*: Add whitespace around '<<'

Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

9 files changed, 16 insertions, 16 deletions

diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc
index 857873a682..8038177c7c 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -40,7 +40,7 @@ cache_as_ram_setup:
   /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
 
   movl %cr4, %eax
-  orl $(3<<9), %eax
+  orl $(3 << 9), %eax
   movl %eax, %cr4
 
   post_code(0xa1)
diff --git a/src/cpu/amd/agesa/cache_as_ram_legacy.inc b/src/cpu/amd/agesa/cache_as_ram_legacy.inc
index c0a69ec74a..55480070c9 100644
--- a/src/cpu/amd/agesa/cache_as_ram_legacy.inc
+++ b/src/cpu/amd/agesa/cache_as_ram_legacy.inc
@@ -43,7 +43,7 @@ cache_as_ram_setup:
   /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
 
   movl %cr4, %eax
-  orl $(3<<9), %eax
+  orl $(3 << 9), %eax
   movl %eax, %cr4
 
   /* Get the cpu_init_detected */
diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index 1c003c8319..693ceb87cd 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -59,7 +59,7 @@ static void enable_apic_ext_id(int nodes)
 		uint32_t val;
 		dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));
 		val = pci_read_config32(dev, 0x68);
-		val |= (1<<17)|(1<<18);
+		val |= (1 << 17)|(1 << 18);
 		pci_write_config32(dev, 0x68, val);
 	}
 }
@@ -84,7 +84,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
 
 	if (bsp_apic_id > 0) { // IOAPIC could start from 0
 		return 0;
-	} else if (pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) )  { // enabled ext id but bsp = 0
+	} else if (pci_read_config32(dev, 0x68) & ( (1 << 17) | (1 << 18)) )  { // enabled ext id but bsp = 0
 		return 1;
 	}
 
diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c
index 83302ca9fe..1f25668c54 100644
--- a/src/cpu/amd/dualcore/dualcore.c
+++ b/src/cpu/amd/dualcore/dualcore.c
@@ -48,11 +48,11 @@ static inline void real_start_other_core(unsigned nodeid)
 	uint32_t dword;
 	// set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0
 	dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44);
-	dword |= 1<<27; // NbMcaToMstCpuEn bit
+	dword |= 1 << 27; // NbMcaToMstCpuEn bit
 	pci_write_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44, dword);
 	// set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
 	dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68);
-	dword |= 1<<5;
+	dword |= 1 << 5;
 	pci_write_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68, dword);
 }
 
diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c
index 80ce1c7c73..e7af552dcb 100644
--- a/src/cpu/amd/dualcore/dualcore_id.c
+++ b/src/cpu/amd/dualcore/dualcore_id.c
@@ -43,14 +43,14 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54)
 		//   when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24]
 		id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
 		id.nodeid = (id.coreid>>CORE_ID_BIT);
-		id.coreid &= ((1<<CORE_ID_BIT)-1);
+		id.coreid &= ((1 << CORE_ID_BIT)-1);
 	}
 	else
 	{
 		// when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]
 		id.nodeid = (cpuid_ebx(1) >> 24) & 0xf;
 		id.coreid = (id.nodeid>>NODE_ID_BIT);
-		id.nodeid &= ((1<<NODE_ID_BIT)-1);
+		id.nodeid &= ((1 << NODE_ID_BIT)-1);
 	}
 	return id;
 }
diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c
index af7ddf349f..cf2b79d8be 100644
--- a/src/cpu/amd/geode_gx2/cpubug.c
+++ b/src/cpu/amd/geode_gx2/cpubug.c
@@ -54,8 +54,8 @@ static void pcideadlock(void)
 	 * for PCI writes to complete.
 	 */
 	msr = rdmsr(CPU_DM_CONFIG0);
-	msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
-	msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
+	msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
+	msr.hi |= (2 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
 	msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
 	wrmsr(CPU_DM_CONFIG0, msr);
 
@@ -126,7 +126,7 @@ static void eng1398(void)
 	msr = rdmsr(MSR_GLCP+0x17);
 	if ((msr.lo & 0xff) <= CPU_REV_2_0) {
 		msr = rdmsr(GLCP_SYS_RSTPLL);
-		if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
+		if (msr.lo & (1 << RSTPPL_LOWER_SDRMODE_SHIFT))
 			return;
 	}
 
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 106cb7949d..8cb6658d18 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -54,8 +54,8 @@ void setup_bsp_ramtop(void)
 	    "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
 	     __func__, msr2.lo, msr2.hi);
 
-	amd_topmem = (uint64_t) msr.hi<<32 | msr.lo;
-	amd_topmem2 = (uint64_t) msr2.hi<<32 | msr2.lo;
+	amd_topmem = (uint64_t) msr.hi << 32 | msr.lo;
+	amd_topmem2 = (uint64_t) msr2.hi << 32 | msr2.lo;
 }
 
 static void setup_ap_ramtop(void)
@@ -128,7 +128,7 @@ void amd_setup_mtrrs(void)
 
 	/* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */
 	sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB);
-	if (bsp_topmem2() > (uint64_t)1<<32) {
+	if (bsp_topmem2() > (uint64_t)1 << 32) {
 		sys_cfg.lo |= SYSCFG_MSR_TOM2En;
 		if (has_tom2wb)
 			sys_cfg.lo |= SYSCFG_MSR_TOM2WB;
diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc
index c0a69ec74a..55480070c9 100644
--- a/src/cpu/amd/pi/cache_as_ram.inc
+++ b/src/cpu/amd/pi/cache_as_ram.inc
@@ -43,7 +43,7 @@ cache_as_ram_setup:
   /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
 
   movl %cr4, %eax
-  orl $(3<<9), %eax
+  orl $(3 << 9), %eax
   movl %eax, %cr4
 
   /* Get the cpu_init_detected */
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
index c4eb50cd2c..a04ec558c0 100644
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ b/src/cpu/amd/quadcore/amd_sibling.c
@@ -64,7 +64,7 @@ static void enable_apic_ext_id(u32 nodes)
 		u32 val;
 		dev = get_node_pci(nodeid, 0);
 		val = pci_read_config32(dev, 0x68);
-		val |= (1<<17)|(1<<18);
+		val |= (1 << 17)|(1 << 18);
 		pci_write_config32(dev, 0x68, val);
 	}
 }