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authorMichał Żygowski <michal.zygowski@3mdeb.com>2019-11-24 16:32:05 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-11 22:47:10 +0000
commit1b12b64dab57151d1f04d13d09c1afbf16a7485f (patch)
treea912c3447ddc7528fa320d8c254c8b403e79cb55 /src/cpu/amd
parentb643d3df8adbc933e02d8c8c7dcc61cc60b65afb (diff)
downloadcoreboot-1b12b64dab57151d1f04d13d09c1afbf16a7485f.tar.xz
AGESA, binaryPI: implement C bootblock
Modify CAR setup to work in bootblock. Provide bootblock C file with necessary C bootblock functions. Additionally chache the ROM and set the MMCONF base before jumping to bootblock main. Change-Id: I29916a96f490ff717c69dc7cd565d74a83dbfb0d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36914 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/amd')
-rw-r--r--src/cpu/amd/agesa/Kconfig8
-rw-r--r--src/cpu/amd/pi/Kconfig8
2 files changed, 16 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 5e1ff1d6c9..2c8f9c5e37 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -49,6 +49,14 @@ config DCACHE_RAM_SIZE
hex
default 0x10000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x4000
+
+config C_ENV_BOOTBLOCK_SIZE
+ hex
+ default 0x8000
+
config ENABLE_MRC_CACHE
bool "Use cached memory configuration"
default n
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index 728c7b1ce7..c534b4d6e8 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -48,6 +48,14 @@ config DCACHE_RAM_SIZE
hex
default 0x10000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x4000
+
+config C_ENV_BOOTBLOCK_SIZE
+ hex
+ default 0x8000
+
endif # CPU_AMD_PI
source "src/cpu/amd/pi/00630F01/Kconfig"