diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-02 13:47:36 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-07-07 01:40:43 +0200 |
| commit | b5e465522ed9efdc3e3f22db6391adb3fbca6bb1 (patch) | |
| tree | 859509af6d34b92e88c1bce41db7b81fe62c9c21 /src/cpu/amd | |
| parent | 46b2271ea49d43607cbed273b367f48cf04d844d (diff) | |
| download | coreboot-b5e465522ed9efdc3e3f22db6391adb3fbca6bb1.tar.xz | |
cpu/amd: Detect any conflicts between sysinfo and the stack region
When increasing the number of supported CPUs on AMD Family 10h/15h
systems there is a relatively high chance of causing a collision
between the CAR global variable region and the AP stack space.
Such collision was noted when increasing the number of supported
CPUs to 32 on the ASUS KGPE-D16.
Detect collision at runtime and print a warning if collision is
present.
Change-Id: Ib5c32f868b1dfffb3b840bb1b1df5f55b5a25f8d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10401
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Diffstat (limited to 'src/cpu/amd')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 3 | ||||
| -rw-r--r-- | src/cpu/amd/geode_gx2/Kconfig | 8 | ||||
| -rw-r--r-- | src/cpu/amd/geode_lx/Kconfig | 8 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/Kconfig | 8 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/init_cpus.c | 8 | ||||
| -rw-r--r-- | src/cpu/amd/socket_754/Kconfig | 8 | ||||
| -rw-r--r-- | src/cpu/amd/socket_940/Kconfig | 8 | ||||
| -rw-r--r-- | src/cpu/amd/socket_S1G1/Kconfig | 8 |
8 files changed, 58 insertions, 1 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 769e5cfaa6..1c22447d2c 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -24,9 +24,10 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) +#define CacheSizeBSPStack CONFIG_DCACHE_BSP_STACK_SIZE /* For CAR with Fam10h. */ -#define CacheSizeAPStack 0x400 /* 1K */ +#define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE #define MSR_MCFG_BASE 0xC0010058 #define MSR_FAM10 0xC001102A diff --git a/src/cpu/amd/geode_gx2/Kconfig b/src/cpu/amd/geode_gx2/Kconfig index e00fea4eac..b867e3701b 100644 --- a/src/cpu/amd/geode_gx2/Kconfig +++ b/src/cpu/amd/geode_gx2/Kconfig @@ -37,6 +37,14 @@ config DCACHE_RAM_SIZE hex default 0x04000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x1000 + +config DCACHE_AP_STACK_SIZE + hex + default 0x400 + config GEODE_VSA bool default y diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index 6001cc75b6..d799d6b394 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -19,6 +19,14 @@ config DCACHE_RAM_SIZE hex default 0x8000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + +config DCACHE_AP_STACK_SIZE + hex + default 0x400 + config GEODE_VSA bool default y diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index cd69caecf3..4b5cdedaa1 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -30,6 +30,14 @@ config DCACHE_RAM_SIZE hex default 0x0c000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + +config DCACHE_AP_STACK_SIZE + hex + default 0x400 + config UDELAY_IO bool default n diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 62ba0b04f1..7e79307c89 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -250,6 +250,14 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) u32 apicid; struct node_core_id id; + uint32_t max_ap_stack_region_size = CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE; + uint32_t bsp_stack_region_lower_boundary = CONFIG_DCACHE_RAM_BASE + (CONFIG_DCACHE_RAM_SIZE / 2); + void * lower_stack_region_boundary = (void*)(bsp_stack_region_lower_boundary - max_ap_stack_region_size); + if (((void*)(sysinfo + 1)) > lower_stack_region_boundary) + printk(BIOS_WARNING, + "sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n", + sysinfo, sysinfo + 1, lower_stack_region_boundary); + /* * already set early mtrr in cache_as_ram.inc */ diff --git a/src/cpu/amd/socket_754/Kconfig b/src/cpu/amd/socket_754/Kconfig index 3ddaea0a9a..395fc788c4 100644 --- a/src/cpu/amd/socket_754/Kconfig +++ b/src/cpu/amd/socket_754/Kconfig @@ -20,4 +20,12 @@ config DCACHE_RAM_SIZE hex default 0x08000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + +config DCACHE_AP_STACK_SIZE + hex + default 0x400 + endif # CPU_AMD_SOCKET_754 diff --git a/src/cpu/amd/socket_940/Kconfig b/src/cpu/amd/socket_940/Kconfig index 1ca23e7410..a481ded55a 100644 --- a/src/cpu/amd/socket_940/Kconfig +++ b/src/cpu/amd/socket_940/Kconfig @@ -21,4 +21,12 @@ config DCACHE_RAM_SIZE hex default 0x08000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + +config DCACHE_AP_STACK_SIZE + hex + default 0x400 + endif # CPU_AMD_SOCKET_940 diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig index f88f64a9cd..2c79e1fca5 100644 --- a/src/cpu/amd/socket_S1G1/Kconfig +++ b/src/cpu/amd/socket_S1G1/Kconfig @@ -31,4 +31,12 @@ config DCACHE_RAM_SIZE hex default 0x08000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + +config DCACHE_AP_STACK_SIZE + hex + default 0x400 + endif |