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author | Ronald G. Minnich <rminnich@gmail.com> | 2005-09-12 15:20:28 +0000 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2005-09-12 15:20:28 +0000 |
commit | e50570112facc2e80d4456f0a21dbe3e85491453 (patch) | |
tree | d52a69b501df988523091b2295962ec222e58553 /src/cpu/amd | |
parent | e118a047b95112c1d1a28be43e151c1123aa07de (diff) | |
download | coreboot-e50570112facc2e80d4456f0a21dbe3e85491453.tar.xz |
sc520 now builds fine. On to testing.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd')
-rw-r--r-- | src/cpu/amd/sc520/raminit.c | 6 | ||||
-rw-r--r-- | src/cpu/amd/sc520/sc520.c | 13 |
2 files changed, 19 insertions, 0 deletions
diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c index b35a2677f7..e1975b721c 100644 --- a/src/cpu/amd/sc520/raminit.c +++ b/src/cpu/amd/sc520/raminit.c @@ -345,6 +345,12 @@ void sc520_udelay(int microseconds) { ; } +/* looks like we define this now */ +void +udelay(int microseconds) { + sc520_udelay(microseconds); +} + static void dumpram(void){ print_err("ctl "); print_err_hex8(*drcctl); print_err("\r\n"); diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c index 7776e82cc8..8a0334bbb3 100644 --- a/src/cpu/amd/sc520/sc520.c +++ b/src/cpu/amd/sc520/sc520.c @@ -10,6 +10,19 @@ #include <bitops.h> #include "chip.h" + +/* hack for now */ +void sc520_udelay(int microseconds) { + volatile int x; + for(x = 0; x < 1000; x++) + ; +} + +/* looks like we define this now */ +void +udelay(int microseconds) { + sc520_udelay(microseconds); +} /* * set up basic things ... PAR should NOT go here, as it might change with the mainboard. */ |