adding preliminary, and almost certainly wrong, rumba support.

This is just a skeleton, basically, and will most likely not even 
compile yet.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 224 insertions, 0 deletions

diff --git a/src/cpu/amd/model_gx2/Config.lb b/src/cpu/amd/model_gx2/Config.lb
new file mode 100644
index 0000000000..b643d778eb
--- /dev/null
+++ b/src/cpu/amd/model_gx2/Config.lb
@@ -0,0 +1,6 @@
+dir /cpu/x86/tsc
+dir /cpu/x86/fpu
+dir /cpu/x86/mmx
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+driver model_gx2_init.o
diff --git a/src/cpu/amd/model_gx2/cpu_setup.inc b/src/cpu/amd/model_gx2/cpu_setup.inc
new file mode 100644
index 0000000000..ff35d3b570
--- /dev/null
+++ b/src/cpu/amd/model_gx2/cpu_setup.inc
@@ -0,0 +1,70 @@
+/*
+    freebios/src/northbridge/nsc/gx1/cpu_setup.inc
+
+    Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
+
+    Initialize the GX1 CPU configuration registers
+*/
+
+/* copied for gx2 for ron minnich, as a placeholder */
+
+/* USES: esi, ecx, eax */
+
+#include <cpu/amd/gx2def.h>
+
+	movl %eax, %ebp /* preserve bist */
+
+cpu_setup_start:
+	leal	cpu_setup_table, %esi
+	movl	$cpu_setup_len, %ecx
+
+cpu_setup_loop:
+	movw	(%esi), %ax
+	addl	$2, %esi
+	outb	%al, $0x22
+	movb	%ah, %al
+	outb	%al, $0x23
+	loop	cpu_setup_loop
+
+	movb	$0xff, %al		/* DIR1 -- Identification Register 1 */
+	outb	%al, $0x22
+	inb	$0x23, %al
+	cmpb	$0x63, %al		/* Revision for GXLV rev 3 */
+	jbe	cpu_no_ccr4
+
+	movb	$0xe8, %al		/* CCR4 */
+	outb	%al, $0x22
+	inb	$0x23, %al
+	orb	$0x20, %al		/* Enable FPU Fast Mode */
+	outb	%al, $0x23
+
+	movb	$0xf0, %al		/* PCR1 --- Performace Control  */
+	outb	%al, $0x22
+	inb	$0x23, %al
+	orb	$0x02, %al		/* Incrementor on, whatever that is */
+	outb	%al, $0x23
+
+	movb	$0x20, %al		/* PCR0 --- Performace Control  */
+	outb	%al, $0x22
+	inb	$0x23, %al
+	orb	$0x20, %al		/* Must be 1 according to data book */
+	orb	$0x04, %al		/* Incrementor Margin 10 */
+	outb	%al, $0x23
+cpu_no_ccr4:
+
+	jmp	cpu_setup_end
+
+cpu_setup_table:
+	.byte	0xc1, 0x00		/* NO SMIs */
+	.byte	0xc3, 0x14		/* Enable CPU config register */
+	.byte	0x20, 0x00
+	.byte	0xb8, GX_BASE>>30	/* Enable GXBASE address */
+	.byte	0xc2, 0x00
+	.byte	0xe8, 0x98
+	.byte	0xc3, 0xf8		/* Enable CPU config register */
+cpu_setup_len = (.-cpu_setup_table)/2
+
+cpu_setup_end:
+	nop
+
+	movl %ebp, %eax	/* Restore bist */
diff --git a/src/cpu/amd/model_gx2/gx_setup.inc b/src/cpu/amd/model_gx2/gx_setup.inc
new file mode 100644
index 0000000000..ce9d46d374
--- /dev/null
+++ b/src/cpu/amd/model_gx2/gx_setup.inc
@@ -0,0 +1,47 @@
+/*
+    freebios/src/northbridge/nsc/gx2/gx_setup.inc
+
+    Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
+
+    Setup the GX_BASE registers on a National Semiconductor Geode CPU
+*/
+
+#include <cpu/amd/gx2def.h>
+
+	movl %eax, %ebp /* Preserve bist */
+
+gx_setup_start:
+	leal	gx_setup_table, %esi
+	movl	$gx_setup_len, %ecx
+	movl	$GX_BASE, %edi
+
+gx_setup_loop:
+	movw	(%esi), %di		/* Only read the low word of address */
+	addl	$4, %esi
+	movl	(%esi), %eax		/* Data */
+	addl	$4, %esi
+	movl	%eax, (%edi)
+	loop	gx_setup_loop
+
+	jmp	gx_setup_end
+
+gx_setup_table:
+	/* Allow writes to config registers */
+	.long	DC_UNLOCK, DC_UNLOCK_MAGIC
+	.long	DC_GENERAL_CFG, 0
+	.long	DC_UNLOCK, 0
+
+	.long	BC_DRAM_TOP, 0x3fffffff
+	.long	BC_XMAP_1, 0x60
+	.long	BC_XMAP_2, 0
+	.long	BC_XMAP_3, 0
+
+	.long	MC_BANK_CFG, 0x00700070	/* No DIMMS installed */
+	.long	MC_MEM_CNTRL1, XBUSARB
+	.long	MC_GBASE_ADD, 0x7ff	/* Almost 1GB */
+gx_setup_len = (.-gx_setup_table)/8
+
+gx_setup_end:
+	nop
+
+	movl %ebp, %eax	/* Restore bist */
diff --git a/src/cpu/amd/model_gx2/model_gx1_init.c b/src/cpu/amd/model_gx2/model_gx1_init.c
new file mode 100644
index 0000000000..855887243b
--- /dev/null
+++ b/src/cpu/amd/model_gx2/model_gx1_init.c
@@ -0,0 +1,101 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/cache.h>
+
+#if 0
+#include <cpu/amd/gx2def.h>
+#include <arch/io.h>
+
+static void gx2_cpu_setup(void)
+{
+	unsigned char rreg;
+	unsigned char cpu_table[] = {
+		0xc1, 0x00,		/* NO SMIs */
+		0xc3, 0x14,		/* Enable CPU config register */
+		0x20, 0x00,		/* */
+		0xb8, GX_BASE>>30,	/* Enable GXBASE address */
+		0xc2, 0x00,
+		0xe8, 0x98,
+		0xc3, 0xf8,		/* Enable CPU config register */
+		0x00, 0x00
+		};
+	unsigned char *cPtr = cpu_table;
+
+	while(rreg = *cPtr++) {
+		unsigned char rval = *cPtr++;
+		outb(rreg, 0x22);
+		outb(rval, 0x23);
+		}
+
+	outb(0xff, 0x22);		/* DIR1 -- Identification register 1 */
+	if(inb(0x23) > 0x63) {		/* Rev greater than R3 */
+		outb(0xe8, 0x22);
+		outb(inb(0x23) | 0x20, 0x23);	/* Enable FPU Fast Mode */
+
+		outb(0xf0, 0x22);
+		outb(inb(0x23) | 0x02, 0x23);	/* Incrementor on */
+
+		outb(0x20, 0x22);
+		outb(inb(0x23) | 0x24, 0x23);	/* Bit 5 must be on */
+						/* Bit 2 Incrementor margin 10 */
+
+	}
+}
+
+static void gx2_gx_setup(void)
+{
+unsigned long gx_setup_table[] = {
+	GX_BASE + DC_UNLOCK, 		DC_UNLOCK_MAGIC,
+	GX_BASE + DC_GENERAL_CFG, 		0,
+	GX_BASE + DC_UNLOCK, 		0,
+	GX_BASE + BC_DRAM_TOP, 		0x3fffffff,
+	GX_BASE + BC_XMAP_1, 		0x60,
+	GX_BASE + BC_XMAP_2, 		0,
+	GX_BASE + BC_XMAP_3, 		0,
+	GX_BASE + MC_BANK_CFG, 		0x00700070,
+	GX_BASE + MC_MEM_CNTRL1, 	XBUSARB,
+	GX_BASE + MC_GBASE_ADD, 	0xff,
+	0, 				0
+	};
+
+unsigned long *gxPtr = gx_setup_table;
+unsigned long *gxdPtr;
+unsigned long addr;
+
+	while(addr = *gxPtr++) {
+		gxdPtr = (unsigned long *)addr;
+		*gxdPtr = *gxPtr++;
+	}
+}
+#endif
+
+static void model_gx2_init(device_t dev)
+{
+#if 0
+	gx2_cpu_setup();
+	gx2_gx_setup();
+#endif
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
+	/* Enable the local cpu apics */
+	setup_lapic();
+};
+
+static struct device_operations cpu_dev_ops = {
+	.init	= model_gx2_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_CYRIX, 0x0540 },
+	{ 0, 0 },
+};
+
+static struct cpu_driver driver __cpu_driver = {
+	.ops	  = &cpu_dev_ops,
+	.id_table = cpu_table,
+};