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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2011-04-11 20:17:22 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2011-04-11 20:17:22 +0000 |
| commit | 5005bb06c17461ef75cd1fef55c24dffaa05e580 (patch) | |
| tree | 2c38986a89152225ad56cb44227f5bc6ddbecd06 /src/cpu/amd | |
| parent | 1fa61ebb3344105ae633ed7eb1be05cc574b666c (diff) | |
| download | coreboot-5005bb06c17461ef75cd1fef55c24dffaa05e580.tar.xz | |
Unify use of post_code
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd')
| -rw-r--r-- | src/cpu/amd/model_gx2/cache_as_ram.inc | 5 | ||||
| -rw-r--r-- | src/cpu/amd/model_lx/cache_as_ram.inc | 5 | ||||
| -rw-r--r-- | src/cpu/amd/sc520/raminit.c | 6 |
3 files changed, 9 insertions, 7 deletions
diff --git a/src/cpu/amd/model_gx2/cache_as_ram.inc b/src/cpu/amd/model_gx2/cache_as_ram.inc index 433576c737..0af2fdf488 100644 --- a/src/cpu/amd/model_gx2/cache_as_ram.inc +++ b/src/cpu/amd/model_gx2/cache_as_ram.inc @@ -27,6 +27,7 @@ #define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ #define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ #include <cpu/amd/gx2def.h> +#include <cpu/x86/post_code.h> /*************************************************************************** /** /** DCacheSetup @@ -184,7 +185,7 @@ done_cache_as_ram_main: /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) /* TODO For suspend/resume the cache will have to live between * CONFIG_RAMBASE and CONFIG_RAMTOP @@ -201,7 +202,7 @@ __main: call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc index a2e8f87e64..a1d775d6d6 100644 --- a/src/cpu/amd/model_lx/cache_as_ram.inc +++ b/src/cpu/amd/model_lx/cache_as_ram.inc @@ -26,6 +26,7 @@ #define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ #define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ #include <cpu/amd/lxdef.h> +#include <cpu/x86/post_code.h> /*************************************************************************** /** /** DCacheSetup @@ -210,7 +211,7 @@ done_cache_as_ram_main: /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) /* TODO For suspend/resume the cache will have to live between * CONFIG_RAMBASE and CONFIG_RAMTOP @@ -227,7 +228,7 @@ __main: call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c index e6232a8eb4..2f7adae190 100644 --- a/src/cpu/amd/sc520/raminit.c +++ b/src/cpu/amd/sc520/raminit.c @@ -144,13 +144,13 @@ void setupsc520(void) /* the 0x80 led should now be working*/ - outb(0xaa, 0x80); + post_code(0xaa); #if 0 - /* wtf are 680 leds ... */ + /* wtf are 680 leds ... *//* <-- WTF is this comment? */ par = (unsigned long *) 0xfffef0c4; *par = 0x28000680; /* well? */ - outb(0x55, 0x80); + post_code(0x55); #endif /* set the uart baud rate clocks to the normal 1.8432 MHz.*/ |