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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-07-08 12:30:02 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-09 09:26:18 +0000 |
| commit | 6c9737b1ac5b71f705350a960dee0e68b9afb440 (patch) | |
| tree | e5c11d8b1586d034b04e2517752c21aaacc3995b /src/cpu/amd | |
| parent | 2106638ec2d7869f396310882bf5e9fa52dbf3c0 (diff) | |
| download | coreboot-6c9737b1ac5b71f705350a960dee0e68b9afb440.tar.xz | |
src/{arch,commonlib,cpu}: Use "foo *bar" instead of "foo* bar"
Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/cpu/amd')
| -rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 2 | ||||
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/init_cpus.c | 4 | ||||
| -rw-r--r-- | src/cpu/amd/pi/romstage.c | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 2fb46d286a..a96811365a 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -121,7 +121,7 @@ static void vErrata343(void) wrmsr(BU_CFG2_MSR, msr); } -asmlinkage void * post_cache_as_ram(void) +asmlinkage void *post_cache_as_ram(void) { uint32_t family = amd_fam1x_cpu_family(); int s3resume = 0; diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 0ecd040253..f1a607b6ea 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -377,7 +377,7 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_STACK_SIZE + CONFIG_DCACHE_BSP_STACK_SLUSH; uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE; uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - max_bsp_stack_region_size; - void * lower_stack_region_boundary = (void*)(bsp_stack_region_lower_boundary - max_ap_stack_region_size); + void *lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary - max_ap_stack_region_size); if (((void*)(sysinfo + 1)) > lower_stack_region_boundary) printk(BIOS_WARNING, "sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n", @@ -825,7 +825,7 @@ static void AMD_SetupPSIVID_d(u32 platform_type, u8 node) * * Returns the offset of the link register. */ -static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset) +static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 *offset) { u32 reg; u32 val; diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c index 9a5fbac003..aa14826149 100644 --- a/src/cpu/amd/pi/romstage.c +++ b/src/cpu/amd/pi/romstage.c @@ -28,7 +28,7 @@ void asmlinkage early_all_cores(void) amd_initmmio(); } -void * asmlinkage romstage_main(unsigned long bist) +void *asmlinkage romstage_main(unsigned long bist) { int s3resume = 0; u8 initial_apic_id = cpuid_ebx(1) >> 24; @@ -45,7 +45,7 @@ void * asmlinkage romstage_main(unsigned long bist) stack_top += HIGH_ROMSTAGE_STACK_SIZE; printk(BIOS_DEBUG, "Move CAR stack.\n"); - return (void*)stack_top; + return (void *)stack_top; } void asmlinkage romstage_after_car(void) |