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authorYinghai Lu <yinghailu@gmail.com>2005-12-09 01:58:07 +0000
committerYinghai Lu <yinghailu@gmail.com>2005-12-09 01:58:07 +0000
commitf42e1770f968adbb4d197917d130219d193081a3 (patch)
treeea7cac9f38341dc146a7886a809bb2caeab58915 /src/cpu/amd
parent653ee54a88b4cb45ec22cb3e986043d900b8564a (diff)
downloadcoreboot-f42e1770f968adbb4d197917d130219d193081a3.tar.xz
make clear_1m_ram.c to support gcc 3 and gcc4
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd')
-rw-r--r--src/cpu/amd/car/clear_1m_ram.c103
1 files changed, 57 insertions, 46 deletions
diff --git a/src/cpu/amd/car/clear_1m_ram.c b/src/cpu/amd/car/clear_1m_ram.c
index eabb6db0fe..d4c6600247 100644
--- a/src/cpu/amd/car/clear_1m_ram.c
+++ b/src/cpu/amd/car/clear_1m_ram.c
@@ -3,58 +3,69 @@
static inline __attribute__((always_inline)) void clear_1m_ram(void)
{
__asm__ volatile (
- /* disable cache */
- "movl %cr0, %eax\n\t"
- "orl $(0x1<<30),%eax\n\t"
- "movl %eax, %cr0\n\t"
- );
- /* enable caching for first 1M using variable mtrr */
- __asm__ volatile (
- "wrmsr"
- : /* No outputs */
- : "c" (0x200), "a" (0 | MTRR_TYPE_WRCOMB), "d" (0)
- );
+ /* disable cache */
+ "movl %%cr0, %%eax\n\t"
+ "orl $(0x1<<30),%%eax\n\t"
+ "movl %%eax, %%cr0\n\t"
- __asm__ volatile (
- "wrmsr"
- : /* No outputs */
- : "c" (0x201), "a" ((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800), "d" (0x0000000f)
- );
+ /* enable caching for first 1M using variable mtrr */
+ "movl $0x200, %%ecx\n\t"
+ "xorl %%edx, %%edx\n\t"
+ "movl $(0 | 1), %%eax\n\t"
+// "movl $(0 | MTRR_TYPE_WRCOMB), %%eax\n\t"
+ "wrmsr\n\t"
+
+ "movl $0x201, %%ecx\n\t"
+ "movl $0x0000000f, %%edx\n\t"
+#if CONFIG_USE_INIT
+ "movl %%esi, %%eax\n\t"
+#else
+ "movl $((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800), %%eax\n\t"
+#endif
+ "wrmsr\n\t"
- __asm__ volatile(
- /* clear the first 1M */
- "cld\n\t"
- "rep stosl\n\t"
- :
- : "a"(0), "D"(0) ,"c" ((CONFIG_LB_MEM_TOPK<<10)>>2)
- );
-
- __asm__ volatile (
- /* disable cache */
- "movl %cr0, %eax\n\t"
- "orl $(0x1<<30),%eax\n\t"
- "movl %eax, %cr0\n\t"
- );
+ /* clear the first 1M */
+#if CONFIG_USE_INIT
+ "movl %%edi, %%ecx\n\t"
+#else
+ "movl $((CONFIG_LB_MEM_TOPK<<10)>>2), %%ecx\n\t"
+#endif
+ "xorl %%edi, %%edi\n\t"
+ "cld\n\t"
+ "xorl %%eax, %%eax\n\t"
+ "rep stosl\n\t"
+
+ /* disable cache */
+ "movl %%cr0, %%eax\n\t"
+ "orl $(0x1<<30),%%eax\n\t"
+ "movl %%eax, %%cr0\n\t"
/* enable caching for first 1M using variable mtrr */
- __asm__ volatile (
- "wrmsr"
- : /* No outputs */
- : "c" (0x200), "a" (0 | MTRR_TYPE_WRBACK), "d" (0)
- );
+ "movl $0x200, %%ecx\n\t"
+ "xorl %%edx, %%edx\n\t"
+ "movl $(0 | 6), %%eax\n\t"
+// "movl $(0 | MTRR_TYPE_WRBACK), %%eax\n\t"
+ "wrmsr\n\t"
- __asm__ volatile (
- "wrmsr"
- : /* No outputs */
- : "c" (0x201), "a" ((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800), "d" (0x0000000f)
- );
+ "movl $0x201, %%ecx\n\t"
+ "movl $0x0000000f, %%edx\n\t"
+#if CONFIG_USE_INIT
+ "movl %%esi, %%eax\n\t"
+#else
+ "movl $((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800), %%eax\n\t"
+#endif
+ "wrmsr\n\t"
- __asm__ volatile (
- /* enable cache */
- "movl %cr0, %eax\n\t"
- "andl $0x9fffffff,%eax\n\t"
- "movl %eax, %cr0\n\t"
- "invd\n\t"
+ /* enable cache */
+ "movl %%cr0, %%eax\n\t"
+ "andl $0x9fffffff,%%eax\n\t"
+ "movl %%eax, %%cr0\n\t"
+ "invd\n\t"
+ :
+ :
+#if CONFIG_USE_INIT
+ "S"((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800), "D" ((CONFIG_LB_MEM_TOPK<<10)>>2)
+#endif
);
}