diff options
| author | Patrick Georgi <patrick@georgi-clan.de> | 2011-10-31 17:07:52 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-11-01 19:06:23 +0100 |
| commit | 784544b934d67dc85ccfcf33e04ff148045836ad (patch) | |
| tree | 8f120ca06da0b126f09526d8814708b95ea6259f /src/cpu/amd | |
| parent | 36c04e8a5c54b100a505650218419e112ccc266e (diff) | |
| download | coreboot-784544b934d67dc85ccfcf33e04ff148045836ad.tar.xz | |
Remove XIP_ROM_BASE
The base is now calculated automatically, and all mentions of that
config option were typical anyway (4GB - XIP_ROM_SIZE).
Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd')
| -rwxr-xr-x | src/cpu/amd/agesa/family10/Kconfig | 4 | ||||
| -rwxr-xr-x | src/cpu/amd/agesa/family12/Kconfig | 5 | ||||
| -rw-r--r-- | src/cpu/amd/agesa/family14/Kconfig | 5 | ||||
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 4 | ||||
| -rw-r--r-- | src/cpu/amd/socket_AM2r2/Kconfig | 5 | ||||
| -rw-r--r-- | src/cpu/amd/socket_AM3/Kconfig | 5 | ||||
| -rw-r--r-- | src/cpu/amd/socket_ASB2/Kconfig | 5 | ||||
| -rw-r--r-- | src/cpu/amd/socket_C32/Kconfig | 5 | ||||
| -rw-r--r-- | src/cpu/amd/socket_F_1207/Kconfig | 5 |
9 files changed, 2 insertions, 41 deletions
diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index 81070e5534..abaa898b38 100755 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -40,10 +40,6 @@ config CDB hex default 0x18 -config XIP_ROM_BASE - hex - default 0xfff80000 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index 5679396f18..c53ee57409 100755 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -57,11 +57,6 @@ config CDB default 0x18 depends on CPU_AMD_AGESA_FAMILY12 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_AGESA_FAMILY12 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 8f3e766e6f..702270c1cc 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -57,11 +57,6 @@ config CDB default 0x18 depends on CPU_AMD_AGESA_FAMILY14 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_AGESA_FAMILY14 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index b9e02f3b8f..955aec9514 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -279,7 +279,7 @@ clear_fixed_var_mtrr_out: movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax wrmsr -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) +#if CONFIG_XIP_ROM_SIZE /* Enable write base caching so we can do execute in place (XIP) * on the flash ROM. @@ -302,7 +302,7 @@ clear_fixed_var_mtrr_out: wbcache_post_fam10_setup: movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr -#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE */ /* Set the default memory type and enable fixed and variable MTRRs. */ movl $MTRRdefType_MSR, %ecx diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig index c7cff14c04..ae4d45866d 100644 --- a/src/cpu/amd/socket_AM2r2/Kconfig +++ b/src/cpu/amd/socket_AM2r2/Kconfig @@ -30,11 +30,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_AM2R2 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_AM2R2 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig index c718eadba6..ed656f13b2 100644 --- a/src/cpu/amd/socket_AM3/Kconfig +++ b/src/cpu/amd/socket_AM3/Kconfig @@ -30,11 +30,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_AM3 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_AM3 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig index 964a59f706..7784a8d4df 100644 --- a/src/cpu/amd/socket_ASB2/Kconfig +++ b/src/cpu/amd/socket_ASB2/Kconfig @@ -30,11 +30,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_ASB2 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_ASB2 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig index 7ffa374962..56324dc776 100644 --- a/src/cpu/amd/socket_C32/Kconfig +++ b/src/cpu/amd/socket_C32/Kconfig @@ -30,11 +30,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_C32 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_C32 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig index 224059a1a1..df9856661c 100644 --- a/src/cpu/amd/socket_F_1207/Kconfig +++ b/src/cpu/amd/socket_F_1207/Kconfig @@ -29,11 +29,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_F_1207 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_F_1207 - config XIP_ROM_SIZE hex default 0x80000 |