src/cpu: Capitalize CPU, APIC and IOAPIC typo fix

Change-Id: I82e0736dc6b44cfcc57cdfdc786c85c4b6882260
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16276
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker

18 files changed, 26 insertions, 26 deletions

diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c
index 22a92e1e3c..ef7072580b 100644
--- a/src/cpu/amd/agesa/family10/model_10_init.c
+++ b/src/cpu/amd/agesa/family10/model_10_init.c
@@ -57,7 +57,7 @@ static void model_10_init(device_t dev)
 
 	enable_cache();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 	/* Set the processor name string */
diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index a0b9479fea..2fc943cda3 100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -62,7 +62,7 @@ static void model_12_init(device_t dev)
 
 	enable_cache();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 	/* Set the processor name string */
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 84ce755501..5e8c9de44b 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -82,7 +82,7 @@ static void model_14_init(device_t dev)
 		wrmsr(MCI_STATUS + (i * 4), msr);
 	}
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c
index 525959f576..7df915382a 100644
--- a/src/cpu/amd/agesa/family15/model_15_init.c
+++ b/src/cpu/amd/agesa/family15/model_15_init.c
@@ -67,7 +67,7 @@ static void model_15_init(device_t dev)
 		wrmsr(MCI_STATUS + (i * 4), msr);
 	}
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
diff --git a/src/cpu/amd/agesa/family15rl/model_15_init.c b/src/cpu/amd/agesa/family15rl/model_15_init.c
index 0492be347b..b28ad57183 100644
--- a/src/cpu/amd/agesa/family15rl/model_15_init.c
+++ b/src/cpu/amd/agesa/family15rl/model_15_init.c
@@ -81,7 +81,7 @@ static void model_15_init(device_t dev)
 		wrmsr(MCI_STATUS + (i * 4), msr);
 	}
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 27aedafd7b..5153a8b343 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -80,7 +80,7 @@ static void model_15_init(device_t dev)
 		wrmsr(MCI_STATUS + (i * 4), msr);
 	}
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index 3d3afec326..f62e698bdf 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -79,7 +79,7 @@ static void model_16_init(device_t dev)
 	}
 
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index e0723ce011..b4f1ad32a9 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -82,7 +82,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
 
 	siblings = get_max_siblings(nodes);
 
-	if(bsp_apic_id > 0) { // io apic could start from 0
+	if (bsp_apic_id > 0) { // IOAPIC could start from 0
 		return 0;
 	} else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) )  { // enabled ext id but bsp = 0
 		return 1;
@@ -108,8 +108,8 @@ unsigned get_apicid_base(unsigned ioapic_num)
 
 	if((!disable_siblings) && (siblings>0) ) {
 		/* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel
-		and the kernel will try to get one that is small than 16 to make io apic work.
-		I don't know when the kernel can support 256 apic id. (APIC_EXT_ID is enabled) */
+		and the kernel will try to get one that is small than 16 to make IOAPIC work.
+		I don't know when the kernel can support 256 APIC id. (APIC_EXT_ID is enabled) */
 
 	        //4:10 for two way  8:12 for four way 16:16 for eight way
 		//Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency?
@@ -122,7 +122,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
 
 	if((apicid_base+ioapic_num-1)>0xf) {
 		// We need to enable APIC EXT ID
-		printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n");
+		printk(BIOS_INFO, "if the IOAPIC device doesn't support 256 APIC id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for IOAPIC\n");
 		enable_apic_ext_id(nodes);
 	}
 
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
index 6fefc3bad0..4405e3cf95 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
@@ -419,7 +419,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
 	if (initial_apicid != 0)	// other than bsp
 #endif
 	{
-		/* use initial apic id to lift it */
+		/* use initial APIC id to lift it */
 		u32 dword = lapic_read(LAPIC_ID);
 		dword &= ~(0xff << 24);
 		dword |=
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index a41374d8ed..f8e6a27bdb 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -133,7 +133,7 @@ static void model_10xxx_init(device_t dev)
 
 	enable_cache();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 	/* Set the processor name string */
diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c
index b6bad4d068..531a362ff5 100644
--- a/src/cpu/amd/geode_gx2/geode_gx2_init.c
+++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c
@@ -22,7 +22,7 @@ static void geode_gx2_init(device_t dev)
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	//setup_lapic();
 
 	vsm_end_post_smi();
diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c
index 335caa3c4a..8ff5848c74 100644
--- a/src/cpu/amd/geode_lx/geode_lx_init.c
+++ b/src/cpu/amd/geode_lx/geode_lx_init.c
@@ -40,7 +40,7 @@ static void geode_lx_init(device_t dev)
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	//setup_lapic();
 
 	// do VSA late init
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 2ea4fb9424..63c88232bf 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -54,7 +54,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
 		j = ((pci_read_config32(PCI_DEV(0, 0x18 + i, 3), 0xe8) >> 12) &
 		     3);
 		if (nb_cfg_54) {
-			if (j == 0) {	// if it is single core, we need to increase siblings for apic calculation
+			if (j == 0) {	// if it is single core, we need to increase siblings for APIC calculation
 #if !CONFIG_K8_REV_F_SUPPORT
 				e0_later_single_core = is_e0_later_in_bsp(i);	// single core
 #else
@@ -266,7 +266,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
 	if (initial_apicid != 0)	// other than bsp
 #endif
 	{
-		/* use initial apic id to lift it */
+		/* use initial APIC id to lift it */
 		u32 dword = lapic_read(LAPIC_ID);
 		dword &= ~(0xff << 24);
 		dword |=
@@ -300,7 +300,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
 
 	if (id.coreid == 0) {
 		distinguish_cpu_resets(id.nodeid);
-//            start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set
+//            start_other_core(id.nodeid); // start second core in first CPU, only allowed for nb_cfg_54 is not set
 	}
 	//here don't need to wait
 	lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33);	// mark the CPU is started
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index e22eae4150..3d69dcba96 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -508,7 +508,7 @@ static void model_fxx_init(device_t dev)
 	/* Set the processor name string */
 	init_processor_name();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 #if CONFIG_LOGICAL_CPUS
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
index 7c4d1712b5..afbade4c1a 100644
--- a/src/cpu/amd/pi/00630F01/model_15_init.c
+++ b/src/cpu/amd/pi/00630F01/model_15_init.c
@@ -79,7 +79,7 @@ static void model_15_init(device_t dev)
 	}
 
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 #if CONFIG_LOGICAL_CPUS
diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
index de7ee384fc..e252c3d849 100644
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ b/src/cpu/amd/pi/00660F01/model_15_init.c
@@ -94,7 +94,7 @@ static void model_15_init(device_t dev)
 	}
 
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 #if CONFIG_LOGICAL_CPUS
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 6cb3009673..a9751a2c2e 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -77,7 +77,7 @@ static void model_16_init(device_t dev)
 	}
 
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 #if CONFIG_LOGICAL_CPUS
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
index 397a3ddb96..f45f34e452 100644
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ b/src/cpu/amd/quadcore/amd_sibling.c
@@ -82,7 +82,7 @@ u32 get_apicid_base(u32 ioapic_num)
 
 	siblings = get_max_siblings(sysconf.nodes);
 
-	if(sysconf.bsp_apicid > 0) { // io apic could start from 0
+	if(sysconf.bsp_apicid > 0) { // IOAPIC could start from 0
 		return 0;
 	} else if (sysconf.enabled_apic_ext_id)	{ // enabled ext id but bsp = 0
 		return 1;
@@ -96,8 +96,8 @@ u32 get_apicid_base(u32 ioapic_num)
 	if((!disable_siblings) && (siblings>0) ) {
 		/* for 8 way dual core, we will used up apicid 16:16, actually
 		   16 is not allowed by current kernel and the kernel will try
-		   to get one that is small than 16 to make io apic work. I don't
-		   know when the kernel can support 256 apic id.
+		   to get one that is small than 16 to make IOAPIC work. I don't
+		   know when the kernel can support 256 APIC id.
 		   (APIC_EXT_ID is enabled) */
 
 		//4:10 for two way  8:12 for four way 16:16 for eight way
@@ -110,7 +110,7 @@ u32 get_apicid_base(u32 ioapic_num)
 
 	if((apicid_base+ioapic_num-1)>0xf) {
 		// We need to enable APIC EXT ID
-		printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\n");
+		printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n");
 		enable_apic_ext_id(sysconf.nodes);
 	}