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authorArne Georg Gleditsch <arne.gleditsch@numascale.com>2010-09-17 00:13:52 +0000
committerMarc Jones <marc.jones@amd.com>2010-09-17 00:13:52 +0000
commit01d56d4276c800f4aa53acd657aed24676a52f4d (patch)
treeadc2356866a07e7d3f429b6e15feedbeb532bc01 /src/cpu/amd
parent8985ef179be85eda9cc10b23f9c143a47e56a2f7 (diff)
downloadcoreboot-01d56d4276c800f4aa53acd657aed24676a52f4d.tar.xz
Clear bit 35 of msr c001_102a in Fam10 rev C cores.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd')
-rw-r--r--src/cpu/amd/model_10xxx/defaults.h2
-rw-r--r--src/cpu/amd/model_10xxx/model_10xxx_init.c4
2 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index 2fbfbb26fc..9a0e349e0a 100644
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -91,7 +91,7 @@ static const struct {
{ BU_CFG2, AMD_DRBH_Cx , AMD_PTYPE_ALL,
0x00000000, 1 << (35-32),
- 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram() ) */
+ 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() ) */
};
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index 6f61fc37fd..a0e1f6fdbe 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -113,9 +113,11 @@ static void model_10xxx_init(device_t dev)
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
- /* Clear ClLinesToNbDis */
msr = rdmsr(BU_CFG2_MSR);
+ /* Clear ClLinesToNbDis */
msr.lo &= ~(1 << 15);
+ /* Clear bit 35 as per Erratum 343 */
+ msr.hi &= ~(1 << (35-32));
wrmsr(BU_CFG2_MSR, msr);
/* Write protect SMM space with SMMLOCK. */