AGESA: Drop old ACPI S3 resume path

Fixed ACPI S3 support will use POSTCAR_STAGE and no longer
uses the code removed here.

Change-Id: I180adaaccce5f0caabcdcd67f3000a21295b0ecf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 0 insertions, 60 deletions

diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index d9c5f704e0..2a34ee041f 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -18,7 +18,6 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
 
-romstage-y += s3_resume.c
 ramstage-y += s3_mtrr.c
 
 ifeq ($(CONFIG_AGESA_LEGACY), y)
diff --git a/src/cpu/amd/agesa/romstage.c b/src/cpu/amd/agesa/romstage.c
index 7955345a46..f8b1e439d6 100644
--- a/src/cpu/amd/agesa/romstage.c
+++ b/src/cpu/amd/agesa/romstage.c
@@ -17,7 +17,6 @@
 #include <arch/cpu.h>
 #include <cbmem.h>
 #include <cpu/amd/car.h>
-#include <cpu/amd/agesa/s3_resume.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/mtrr.h>
 #include <console/console.h>
@@ -130,8 +129,5 @@ void asmlinkage romstage_after_car(void)
 	if (HAS_LEGACY_WRAPPER)
 		agesa_postcar(cb);
 
-	if (!IS_ENABLED(CONFIG_CPU_AMD_PI) && cb->s3resume)
-		set_resume_cache();
-
 	run_ramstage();
 }
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
deleted file mode 100644
index 34717b9618..0000000000
--- a/src/cpu/amd/agesa/s3_resume.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/car.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cbmem.h>
-#include <program_loading.h>
-#include <string.h>
-#include <halt.h>
-#include "s3_resume.h"
-#include <northbridge/amd/agesa/agesa_helper.h>
-
-void set_resume_cache(void)
-{
-	msr_t msr;
-
-	/* disable fixed mtrr for now,  it will be enabled by mtrr restore */
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
-	wrmsr(SYSCFG_MSR, msr);
-
-	/* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */
-	msr.lo = 0 | MTRR_TYPE_WRBACK;
-	msr.hi = 0;
-	wrmsr(MTRR_PHYS_BASE(0), msr);
-	msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID;
-	msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
-	wrmsr(MTRR_PHYS_MASK(0), msr);
-
-	/* Set the default memory type and disable fixed and enable variable MTRRs */
-	msr.hi = 0;
-	msr.lo = (1 << 11);
-	wrmsr(MTRR_DEF_TYPE_MSR, msr);
-
-	enable_cache();
-}
diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h
index bb65af3f05..4a7ccb591d 100644
--- a/src/cpu/amd/agesa/s3_resume.h
+++ b/src/cpu/amd/agesa/s3_resume.h
@@ -17,8 +17,6 @@
 #define S3_RESUME_H
 
 void restore_mtrr(void);
-void prepare_for_resume(void);
-void set_resume_cache(void);
 
 void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size);
 const void *OemS3Saved_MTRR_Storage(void);