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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-12-14 19:41:54 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-12-20 07:18:35 +0100
commit4a08e15086e9c7bda4a63e0d3609b74a14293d2b (patch)
tree7f70899232da761b42e7566b677201c1e8670b09 /src/cpu/amd
parent48518f0d60478a9277cd50158fbf28f56ae97532 (diff)
downloadcoreboot-4a08e15086e9c7bda4a63e0d3609b74a14293d2b.tar.xz
AGESA fam14: Add amd_initenv()
Not part of wrapper to AGESA, but workaround for enable_resources(). Also remove remains of comments in non-fam14 wrappers. Change-Id: I2526821ca283feb6a506b602b86f817f8b03b341 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7816 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/cpu/amd')
-rw-r--r--src/cpu/amd/agesa/family14/fixme.c80
1 files changed, 80 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index 8d9a177215..3bcb574daf 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -97,3 +97,83 @@ void amd_initmmio(void)
PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
+
+void amd_initenv(void)
+{
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ PCI_ADDR PciAddress;
+ UINT32 PciValue;
+
+ /* Initialize Subordinate Bus Number and Secondary Bus Number
+ * In platform BIOS this address is allocated by PCI enumeration code
+ Modify D1F0x18
+ */
+ PciAddress.Address.Bus = 0;
+ PciAddress.Address.Device = 1;
+ PciAddress.Address.Function = 0;
+ PciAddress.Address.Register = 0x18;
+ /* Write to D1F0x18 */
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x00010100;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize GMM Base Address for Legacy Bridge Mode
+ * Modify B1D5F0x18
+ */
+ PciAddress.Address.Bus = 1;
+ PciAddress.Address.Device = 5;
+ PciAddress.Address.Function = 0;
+ PciAddress.Address.Register = 0x18;
+
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x96000000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize FB Base Address for Legacy Bridge Mode
+ * Modify B1D5F0x10
+ */
+ PciAddress.Address.Register = 0x10;
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x80000000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize GMM Base Address for Pcie Mode
+ * Modify B0D1F0x18
+ */
+ PciAddress.Address.Bus = 0;
+ PciAddress.Address.Device = 1;
+ PciAddress.Address.Function = 0;
+ PciAddress.Address.Register = 0x18;
+
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x96000000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize FB Base Address for Pcie Mode
+ * Modify B0D1F0x10
+ */
+ PciAddress.Address.Register = 0x10;
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x80000000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize MMIO Base and Limit Address
+ * Modify B0D1F0x20
+ */
+ PciAddress.Address.Bus = 0;
+ PciAddress.Address.Device = 1;
+ PciAddress.Address.Function = 0;
+ PciAddress.Address.Register = 0x20;
+
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x96009600;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize MMIO Prefetchable Memory Limit and Base
+ * Modify B0D1F0x24
+ */
+ PciAddress.Address.Register = 0x24;
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x8FF18001;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+}