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authorDave Frodin <dave.frodin@se-eng.com>2013-02-25 10:39:48 -0700
committerZheng Bao <zheng.bao@amd.com>2013-02-26 03:34:08 +0100
commit502533f656d41632f3b8ec19c385e8efa8c264a6 (patch)
tree4741e32163a47df9e79348beb707de15c171ecc7 /src/cpu/amd
parenta96d24d672abfd2ce91caa2d762fdce3d67da600 (diff)
downloadcoreboot-502533f656d41632f3b8ec19c385e8efa8c264a6.tar.xz
Revert "AMD S3: Program the flash in a bigger data packet"
This reverts commit ca6e1f6c04c96c435bdbf30a1b88cab0e5be330b. The packet size changes ends up corrupting the flash when booting Persimmon. I did figure out that the maximum number of bytes that can be sent is actually 8 bytes according to the sb800 spec. There must be additional problems beyond that since setting the packet size to 8 still causes problems. Change-Id: Ieb24247cf79e95bb0e548c83601dfddffbf6be59 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/2509 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Diffstat (limited to 'src/cpu/amd')
-rw-r--r--src/cpu/amd/agesa/s3_resume.c56
1 files changed, 34 insertions, 22 deletions
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 278c1dadf3..ee9d7c9f2d 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -178,21 +178,29 @@ void OemAgesaSaveMtrr(void)
/* Fixed MTRRs */
msr_data = rdmsr(0x250);
- flash->write(flash, nvram_pos, 8, &msr_data);
- nvram_pos += 8;
+ flash->write(flash, nvram_pos, 4, &msr_data.lo);
+ nvram_pos += 4;
+ flash->write(flash, nvram_pos, 4, &msr_data.hi);
+ nvram_pos += 4;
msr_data = rdmsr(0x258);
- flash->write(flash, nvram_pos, 8, &msr_data);
- nvram_pos += 8;
+ flash->write(flash, nvram_pos, 4, &msr_data.lo);
+ nvram_pos += 4;
+ flash->write(flash, nvram_pos, 4, &msr_data.hi);
+ nvram_pos += 4;
msr_data = rdmsr(0x259);
- flash->write(flash, nvram_pos, 8, &msr_data);
- nvram_pos += 8;
+ flash->write(flash, nvram_pos, 4, &msr_data.lo);
+ nvram_pos += 4;
+ flash->write(flash, nvram_pos, 4, &msr_data.hi);
+ nvram_pos += 4;
for (i = 0x268; i < 0x270; i++) {
msr_data = rdmsr(i);
- flash->write(flash, nvram_pos, 8, &msr_data);
- nvram_pos += 8;
+ flash->write(flash, nvram_pos, 4, &msr_data.lo);
+ nvram_pos += 4;
+ flash->write(flash, nvram_pos, 4, &msr_data.hi);
+ nvram_pos += 4;
}
/* Disable access to AMD RdDram and WrDram extension bits */
@@ -203,24 +211,32 @@ void OemAgesaSaveMtrr(void)
/* Variable MTRRs */
for (i = 0x200; i < 0x210; i++) {
msr_data = rdmsr(i);
- flash->write(flash, nvram_pos, 8, &msr_data);
- nvram_pos += 8;
+ flash->write(flash, nvram_pos, 4, &msr_data.lo);
+ nvram_pos += 4;
+ flash->write(flash, nvram_pos, 4, &msr_data.hi);
+ nvram_pos += 4;
}
/* SYS_CFG */
msr_data = rdmsr(0xC0010010);
- flash->write(flash, nvram_pos, 8, &msr_data);
- nvram_pos += 8;
+ flash->write(flash, nvram_pos, 4, &msr_data.lo);
+ nvram_pos += 4;
+ flash->write(flash, nvram_pos, 4, &msr_data.hi);
+ nvram_pos += 4;
/* TOM */
msr_data = rdmsr(0xC001001A);
- flash->write(flash, nvram_pos, 8, &msr_data);
- nvram_pos += 8;
+ flash->write(flash, nvram_pos, 4, &msr_data.lo);
+ nvram_pos += 4;
+ flash->write(flash, nvram_pos, 4, &msr_data.hi);
+ nvram_pos += 4;
/* TOM2 */
msr_data = rdmsr(0xC001001D);
- flash->write(flash, nvram_pos, 8, &msr_data);
- nvram_pos += 8;
+ flash->write(flash, nvram_pos, 4, &msr_data.lo);
+ nvram_pos += 4;
+ flash->write(flash, nvram_pos, 4, &msr_data.hi);
+ nvram_pos += 4;
flash->spi->rw = SPI_WRITE_FLAG;
spi_release_bus(flash->spi);
@@ -274,17 +290,13 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
flash->erase(flash, S3_DATA_VOLATILE_POS, S3_DATA_VOLATILE_SIZE);
}
-#ifndef SPI_DATA_PACKET_SIZE
-#define SPI_DATA_PACKET_SIZE 0xF
-#endif
nvram_pos = 0;
flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize);
- for (nvram_pos = 0; nvram_pos < DataSize - SPI_DATA_PACKET_SIZE; nvram_pos += SPI_DATA_PACKET_SIZE) {
+ for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) {
data = *(u32 *) (Data + nvram_pos);
- flash->write(flash, nvram_pos + pos + 4, SPI_DATA_PACKET_SIZE, (u8 *)(Data + nvram_pos));
+ flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos));
}
- flash->write(flash, nvram_pos + pos + 4, DataSize % SPI_DATA_PACKET_SIZE, (u8 *)(Data + nvram_pos));
flash->spi->rw = SPI_WRITE_FLAG;
spi_release_bus(flash->spi);