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authorDaniele Forsi <dforsi@gmail.com>2014-07-22 18:00:56 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2014-07-23 09:07:47 +0200
commit53847a211bd78a9cbf838f63f155368c641f7cd5 (patch)
treec0a72d2d52e7b70276aed0bcb15ebd8c794c8031 /src/cpu/amd
parente34a6275eeebf324e921f8aa06e7c1c9fc0179f8 (diff)
downloadcoreboot-53847a211bd78a9cbf838f63f155368c641f7cd5.tar.xz
src/.../Kconfig: various small fixes to texts
Fixed spelling and added empty lines to separate the help from the text automatically added during make menuconfig. Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6313 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/cpu/amd')
-rw-r--r--src/cpu/amd/agesa/Kconfig6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index e982a83770..fcba0cfdb2 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -46,10 +46,10 @@ config XIP_ROM_SIZE
default 0x100000
help
Overwride the default write through caching size as 1M Bytes.
- On some AMD paltform, one socket support 2 or more kinds of
- processor family, compiling several cpu families agesa code
+ On some AMD platforms, one socket supports 2 or more kinds of
+ processor family, compiling several CPU families agesa code
will increase the romstage size.
- In order to execute romstage in place on the flash rom,
+ In order to execute romstage in place on the flash ROM,
more space is required to be set as write through caching.
config UDELAY_LAPIC_FIXED_FSB