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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-23 17:10:27 +0200
committerMartin Roth <martinroth@google.com>2018-10-30 20:18:53 +0000
commit8a643703b87630b4346e52cac3d3acdc95ac1c70 (patch)
treee7ec84129a9c02940b8fd8bbd778601b15c0956a /src/cpu/amd
parent50f2e4ccec9df213e012c7ecddb0a9c644526c8d (diff)
downloadcoreboot-8a643703b87630b4346e52cac3d3acdc95ac1c70.tar.xz
{cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros
Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29243 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/amd')
-rw-r--r--src/cpu/amd/agesa/family12/fixme.c3
-rw-r--r--src/cpu/amd/agesa/family14/fixme.c3
-rw-r--r--src/cpu/amd/agesa/family15tn/fixme.c3
-rw-r--r--src/cpu/amd/agesa/family16kb/fixme.c3
-rw-r--r--src/cpu/amd/family_10h-family_15h/model_10xxx_init.c2
-rw-r--r--src/cpu/amd/pi/00630F01/fixme.c3
-rw-r--r--src/cpu/amd/pi/00660F01/fixme.c3
-rw-r--r--src/cpu/amd/pi/00730F01/fixme.c3
8 files changed, 15 insertions, 8 deletions
diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c
index e97a819fda..9df43e5f61 100644
--- a/src/cpu/amd/agesa/family12/fixme.c
+++ b/src/cpu/amd/agesa/family12/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -40,7 +41,7 @@ void amd_initcpuio(void)
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00DFFF00;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32) MsrReg;
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index 978c25ff6f..a49cefbaa3 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -51,7 +52,7 @@ void amd_initcpuio(void)
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; // last address before non-posted range
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32) MsrReg;
diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c
index 7e493f9dda..a0ae193bcf 100644
--- a/src/cpu/amd/agesa/family15tn/fixme.c
+++ b/src/cpu/amd/agesa/family15tn/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -47,7 +48,7 @@ void amd_initcpuio(void)
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c
index c761d6d22f..2d74c7b769 100644
--- a/src/cpu/amd/agesa/family16kb/fixme.c
+++ b/src/cpu/amd/agesa/family16kb/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -47,7 +48,7 @@ void amd_initcpuio(void)
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index 2374503287..c0316e5dd7 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -90,7 +90,7 @@ static void model_10xxx_init(struct device *dev)
disable_cache();
for (i = 0x2; i < 0x10; i++) {
- wrmsr(0x00000200 | i, msr);
+ wrmsr(MTRR_PHYS_BASE(0) | i, msr);
}
enable_cache();
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
index 11cab62ba8..ae2a2dfe88 100644
--- a/src/cpu/amd/pi/00630F01/fixme.c
+++ b/src/cpu/amd/pi/00630F01/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
#include <AGESA.h>
@@ -52,7 +53,7 @@ void amd_initcpuio(void)
/* last address before non-posted range */
PciData = 0x00FECF00;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
index ee8728d34d..e028b6f85b 100644
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ b/src/cpu/amd/pi/00660F01/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
#include <AGESA.h>
@@ -51,7 +52,7 @@ void amd_initcpuio(void)
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c
index 4350572b9b..163066b6d8 100644
--- a/src/cpu/amd/pi/00730F01/fixme.c
+++ b/src/cpu/amd/pi/00730F01/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
#include <AGESA.h>
@@ -51,7 +52,7 @@ void amd_initcpuio(void)
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 02:36:43 +0000