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authorHung-Te Lin <hungte@chromium.org>2013-02-12 00:07:38 +0800
committerRonald G. Minnich <rminnich@gmail.com>2013-02-12 03:02:45 +0100
commit7635a60ca848b50ff4a0ac85a667adc7151a5abf (patch)
tree42d7db8bd1c1bcacd5d1c4d2b70ca0b8ad3a6da5 /src/cpu/armltd/cortex-a9
parentbc64cae995ddab369289e19b41501df5dbc58751 (diff)
downloadcoreboot-7635a60ca848b50ff4a0ac85a667adc7151a5abf.tar.xz
armv7: Add emulation/qemu-armv7 board.
To simplify testing ARM implementation, we need a QEMU configuration for ARM. The qemu-armv7 provides serial output, CBFS simulation, and full boot path (bootblock, romstage, ramstage) to verify the boot loader functionality. To run with QEMU: export QEMU_AUDIO_DRV=none qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom Verified to boot until ramstage loaded successfully by QEMU v1.0.50. Change-Id: I1f23ffaf408199811a0756236821c7e0f2a85004 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2354 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/armltd/cortex-a9')
-rw-r--r--src/cpu/armltd/cortex-a9/Kconfig5
-rw-r--r--src/cpu/armltd/cortex-a9/Makefile.inc2
-rw-r--r--src/cpu/armltd/cortex-a9/bootblock.c17
-rw-r--r--src/cpu/armltd/cortex-a9/cache.c44
4 files changed, 68 insertions, 0 deletions
diff --git a/src/cpu/armltd/cortex-a9/Kconfig b/src/cpu/armltd/cortex-a9/Kconfig
new file mode 100644
index 0000000000..7f35cfd653
--- /dev/null
+++ b/src/cpu/armltd/cortex-a9/Kconfig
@@ -0,0 +1,5 @@
+config BOOTBLOCK_CPU_INIT
+ string
+ default "cpu/armltd/cortex-a9/bootblock.c"
+ help
+ CPU/SoC-specific bootblock code.
diff --git a/src/cpu/armltd/cortex-a9/Makefile.inc b/src/cpu/armltd/cortex-a9/Makefile.inc
new file mode 100644
index 0000000000..d1e7edfdee
--- /dev/null
+++ b/src/cpu/armltd/cortex-a9/Makefile.inc
@@ -0,0 +1,2 @@
+ramstage-y += cache.c
+romstage-y += cache.c
diff --git a/src/cpu/armltd/cortex-a9/bootblock.c b/src/cpu/armltd/cortex-a9/bootblock.c
new file mode 100644
index 0000000000..8925439d2a
--- /dev/null
+++ b/src/cpu/armltd/cortex-a9/bootblock.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+void bootblock_cpu_init(void);
+void bootblock_cpu_init(void)
+{
+}
diff --git a/src/cpu/armltd/cortex-a9/cache.c b/src/cpu/armltd/cortex-a9/cache.c
new file mode 100644
index 0000000000..957871dba7
--- /dev/null
+++ b/src/cpu/armltd/cortex-a9/cache.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <system.h>
+#include <armv7.h>
+
+/*
+ * Sets L2 cache related parameters before enabling data cache
+ */
+void v7_outer_cache_enable(void)
+{
+}
+
+/* stubs so we don't need weak symbols in cache_v7.c */
+void v7_outer_cache_disable(void)
+{
+}
+
+void v7_outer_cache_flush_all(void)
+{
+}
+
+void v7_outer_cache_inval_all(void)
+{
+}
+
+void v7_outer_cache_flush_range(u32 start, u32 end)
+{
+}
+
+void v7_outer_cache_inval_range(u32 start, u32 end)
+{
+}