diff options
| author | Martin Roth <gaumless@gmail.com> | 2017-10-15 14:20:28 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-15 23:23:17 +0000 |
| commit | 732fb2ab5363968a12b2270319189c2a2a536a36 (patch) | |
| tree | f9fa6c13a18129fbcf40b69d83d46ef4921d3cb8 /src/cpu/dmp/vortex86ex/Kconfig | |
| parent | 99c45dee0ae62254be36a312d67764784450b564 (diff) | |
| download | coreboot-732fb2ab5363968a12b2270319189c2a2a536a36.tar.xz | |
DMP Vortex86ex board & chip: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
soc/dmp/vortex86ex
Mainboards:
mainboard/dmp/vortex86ex
Change-Id: Iee7b6005cc2964b2346aaf4dbd9b2d2112b7403f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/dmp/vortex86ex/Kconfig')
| -rw-r--r-- | src/cpu/dmp/vortex86ex/Kconfig | 76 |
1 files changed, 0 insertions, 76 deletions
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig deleted file mode 100644 index 1af7ec4bf8..0000000000 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ /dev/null @@ -1,76 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 DMP Electronics Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config CPU_DMP_VORTEX86EX - bool - -if CPU_DMP_VORTEX86EX - -config CPU_SPECIFIC_OPTIONS - def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select UDELAY_TSC - -# ROM Strap PLL config setting : - -choice - prompt "ROM Strap PLL config" - default PLL_300_300_33 - -config PLL_200_200_33 - bool "CPU=200Mhz/DRAM=200Mhz/PCI=33Mhz" - -config PLL_300_300_33 - bool "CPU=300Mhz/DRAM=300Mhz/PCI=33Mhz" - -config PLL_300_300_100 - bool "CPU=300Mhz/DRAM=300Mhz/PCI=100Mhz" - -config PLL_400_200_33 - bool "CPU=400Mhz/DRAM=200Mhz/PCI=33Mhz" - -config PLL_400_200_100 - bool "CPU=400Mhz/DRAM=200Mhz/PCI=100Mhz" - -config PLL_400_400_33 - bool "CPU=400Mhz/DRAM=400Mhz/PCI=33Mhz" - -config PLL_500_250_33 - bool "CPU=500Mhz/DRAM=250Mhz/PCI=33Mhz" - -config PLL_500_500_33 - bool "CPU=500Mhz/DRAM=500Mhz/PCI=33Mhz" - -config PLL_400_300_33 - bool "CPU=400Mhz/DRAM=300Mhz/PCI=33Mhz" - -config PLL_400_300_100 - bool "CPU=400Mhz/DRAM=300Mhz/PCI=100Mhz" - -config PLL_444_333_33 - bool "CPU=444Mhz/DRAM=333Mhz/PCI=33Mhz" - -config PLL_466_350_33 - bool "CPU=466Mhz/DRAM=350Mhz/PCI=33Mhz" - -config PLL_500_375_33 - bool "CPU=500Mhz/DRAM=375Mhz/PCI=33Mhz" - -endchoice - -endif |