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| author | Martin Roth <gaumless@gmail.com> | 2015-03-26 22:33:31 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2015-04-29 17:36:24 +0200 |
| commit | e2c2bb944717f808de47a9c473a1885086c64425 (patch) | |
| tree | 5251c333775b82c4491baf3802354d2af452ebe2 /src/cpu/dmp | |
| parent | f20046f5cf682ea0318d4c6d69c2cf05e3a72e76 (diff) | |
| download | coreboot-e2c2bb944717f808de47a9c473a1885086c64425.tar.xz | |
dmp/vortex86: move PLL config to cpu Kconfig
This moves the vortex86ex cpu's pll configuration out of the mainboard
and into the cpu's Kconfig.
Change-Id: I72ee1baa3a96586fceff03ff43c5f61e2498667e
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/9058
Tested-by: build bot (Jenkins)
Reviewed-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/cpu/dmp')
| -rw-r--r-- | src/cpu/dmp/vortex86ex/Kconfig | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig index 080bb6475c..b14be7d64e 100644 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ b/src/cpu/dmp/vortex86ex/Kconfig @@ -24,3 +24,50 @@ config CPU_DMP_VORTEX86EX select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select UDELAY_TSC + +# ROM Strap PLL config setting : + +choice + prompt "ROM Strap PLL config" + default PLL_300_300_33 + +config PLL_200_200_33 + bool "CPU=200Mhz/DRAM=200Mhz/PCI=33Mhz" + +config PLL_300_300_33 + bool "CPU=300Mhz/DRAM=300Mhz/PCI=33Mhz" + +config PLL_300_300_100 + bool "CPU=300Mhz/DRAM=300Mhz/PCI=100Mhz" + +config PLL_400_200_33 + bool "CPU=400Mhz/DRAM=200Mhz/PCI=33Mhz" + +config PLL_400_200_100 + bool "CPU=400Mhz/DRAM=200Mhz/PCI=100Mhz" + +config PLL_400_400_33 + bool "CPU=400Mhz/DRAM=400Mhz/PCI=33Mhz" + +config PLL_500_250_33 + bool "CPU=500Mhz/DRAM=250Mhz/PCI=33Mhz" + +config PLL_500_500_33 + bool "CPU=500Mhz/DRAM=500Mhz/PCI=33Mhz" + +config PLL_400_300_33 + bool "CPU=400Mhz/DRAM=300Mhz/PCI=33Mhz" + +config PLL_400_300_100 + bool "CPU=400Mhz/DRAM=300Mhz/PCI=100Mhz" + +config PLL_444_333_33 + bool "CPU=444Mhz/DRAM=333Mhz/PCI=33Mhz" + +config PLL_466_350_33 + bool "CPU=466Mhz/DRAM=350Mhz/PCI=33Mhz" + +config PLL_500_375_33 + bool "CPU=500Mhz/DRAM=375Mhz/PCI=33Mhz" + +endchoice |