diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2012-10-30 09:03:43 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-14 01:44:40 +0100 |
| commit | 76c3700f02f79b49fec30d6ef18d336f122cbf50 (patch) | |
| tree | cb1c750ef3946e2ae462e1847ec89946579274b2 /src/cpu/intel/Kconfig | |
| parent | cc86e63e835ab0bceb62215460a13266a791cdd3 (diff) | |
| download | coreboot-76c3700f02f79b49fec30d6ef18d336f122cbf50.tar.xz | |
haswell: Add initial support for Haswell platforms
The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore,
the southbridge support is included as well. The basis for this code is
the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires
more attention, but this is a good starting point.
This code partially gets up through the romstage just before training
memory on a Haswell reference board.
Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2616
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/Kconfig')
| -rw-r--r-- | src/cpu/intel/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index c3cf4c9fa3..45071d0c7e 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -16,6 +16,7 @@ source src/cpu/intel/model_f2x/Kconfig source src/cpu/intel/model_f3x/Kconfig source src/cpu/intel/model_f4x/Kconfig source src/cpu/intel/ep80579/Kconfig +source src/cpu/intel/haswell/Kconfig # Sockets/Slots source src/cpu/intel/slot_2/Kconfig source src/cpu/intel/slot_1/Kconfig |