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authorArthur Heymans <arthur@aheymans.xyz>2019-01-11 23:56:51 +0100
committerArthur Heymans <arthur@aheymans.xyz>2019-01-15 11:38:01 +0000
commit19e7273ec2dc243b4089b9aeeaf7929ff5a20a34 (patch)
tree98894887d49e25e325f9d87eb9677e932d112400 /src/cpu/intel/Kconfig
parent0feaa85233c099b06f84d5a0e1d82575efdba56b (diff)
downloadcoreboot-19e7273ec2dc243b4089b9aeeaf7929ff5a20a34.tar.xz
cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup
Pineview CPUs support a non-eviction mode that ought to be used during cache as ram setup. This assumes that all atoms that need to set a special register to enable L2 cache are socketed and hence uses a static Kconfig option to set that MSR on affected CPUs. Tested on Foxconn D41S, still boots. Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30863 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/Kconfig')
-rw-r--r--src/cpu/intel/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index f5d0ab9268..18f73b45d1 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -36,3 +36,4 @@ source src/cpu/intel/fit/Kconfig
source src/cpu/intel/turbo/Kconfig
source src/cpu/intel/common/Kconfig
source src/cpu/intel/microcode/Kconfig
+source src/cpu/intel/car/non-evict/Kconfig