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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-09-26 10:26:49 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-01 15:10:16 +0000 |
| commit | 6e079dc120a4aa95a25cfe536d4b1acd178918fd (patch) | |
| tree | c8b1d76e5dd361964389c0f628b162102e72add1 /src/cpu/intel/Makefile.inc | |
| parent | 5adbc767f66224e617b6c8204a868542b8010999 (diff) | |
| download | coreboot-6e079dc120a4aa95a25cfe536d4b1acd178918fd.tar.xz | |
cpu/intel/common: Move intel_ht_sibling() to common folder
Make intel_ht_sibling() available on all platforms.
Will be used in MP init to only write "Core" MSRs from one thread
on HyperThreading enabled platforms, to prevent race conditions and
resulting #GP if MSRs are written twice or are already locked.
Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/Makefile.inc')
| -rw-r--r-- | src/cpu/intel/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 3f897407cf..484e241312 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -16,3 +16,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 + +subdirs-y += common |