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| author | Marc Jones <marc.jones@se-eng.com> | 2013-10-29 17:46:54 -0600 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2013-12-04 18:45:42 +0100 |
| commit | bdafcfa55509d0cf2cbbb686411f569d56d3916c (patch) | |
| tree | 8a46755738c18acbbfb2678cc6ff76439543bb30 /src/cpu/intel/Makefile.inc | |
| parent | 54b8e7a0bba7787eca737506cb5d85bf408344d2 (diff) | |
| download | coreboot-bdafcfa55509d0cf2cbbb686411f569d56d3916c.tar.xz | |
Add the Intel FSP 206ax CPU core support
Add support for 206ax using the Intel FSP.
The FSP is different enough to warrant its own source files
for now. It has different CAR code, micorcode, and FSP inclusion.
It may be possible to combine this code with the mrc based
solution used by the chromebooks in the future.
Change-Id: I5105631af34e9c3a804ace908c4205f073abb9b4
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4016
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/Makefile.inc')
| -rw-r--r-- | src/cpu/intel/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 54624fb8c7..964369ddd3 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -19,6 +19,8 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE) += fsp_model_206ax +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE) += fsp_model_206ax subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771 |