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authorElyes HAOUAS <ehaouas@noos.fr>2018-09-30 07:44:39 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-04 09:38:04 +0000
commit02820ca1862fdf7078aa0749d3f2ef5c80b0daba (patch)
tree4bf69038ca2831385ab763bb031491283a7e571e /src/cpu/intel/car/p3
parent0562c1e75820b05c4a278538496e8a3ffc660866 (diff)
downloadcoreboot-02820ca1862fdf7078aa0749d3f2ef5c80b0daba.tar.xz
cpu/intel/car: Fix typo
Change-Id: If71ab647f012a735c6aa6939463414407757ab9a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/cpu/intel/car/p3')
-rw-r--r--src/cpu/intel/car/p3/cache_as_ram.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
index b3bf230226..121d169daf 100644
--- a/src/cpu/intel/car/p3/cache_as_ram.S
+++ b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -43,7 +43,7 @@ clear_fixed_mtrr:
wrmsr
jnz clear_fixed_mtrr
- /* Figure put how many MTRRs we have, and clear them out */
+ /* Figure out how many MTRRs we have, and clear them out */
mov $MTRR_CAP_MSR, %ecx
rdmsr
movzb %al, %ebx /* Number of variable MTRRs */